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参数资料
型号： WJLXT971ALE.A4SE000
厂商： CORTINA SYSTEMS INC
元件分类： 网络接口
英文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封装： LEAD FREE, LQFP-64
文件页数： 94/116页
文件大小： 1172K
代理商： WJLXT971ALE.A4SE000
LXT971A 3.3V Dual-Speed Fast Ethernet Transceiver
Datasheet
79
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
Table 49. Auto-Negotiation Expansion (Address 6)
Bit
Name
Description
Type 1
Default
6.15:6
Reserved
Ignore on read.
RO
0
6.5
Base Page
This bit indicates the status of the auto-negotiation
variable base page. It flags synchronization with the
auto-negotiation state diagram, allowing detection of
interrupted links. This bit is only used if Register bit
16.1 (Alternate NP feature) is set.
1 = Base page = true
0 = Base page = false
RO/
LH
0
6.4
Parallel
Detection Fault
1 = Parallel detection fault has occurred.
0 = Parallel detection fault has not occurred.
RO/
LH
0
6.3
Link Partner
Next Page Able
1 = Link partner is next page able.
0 = Link partner is not next page able.
RO
0
6.2
Next Page Able
1 = Local device is next page able.
0 = Local device is not next page able.
RO
1
6.1
Page Received
1 = Indicates that a new page has been received and
the received code word has been loaded into Register
5 (Base Pages) or Register 8 (Next Pages) as specified
in Clause 28 of IEEE 802.3. This bit is cleared on Read.
If Register bit 16.1 is set, the Page Received bit is also
cleared when mr_page_rx = false or transmit_disable =
true.
RO
LH
0
6.0
Link Partner A/N
Able
1 = Link partner is auto-negotiation able.
0 = Link partner is not auto-negotiation able.
RO
0
1. RO = Read Only LH = Latching High
Table 50. Auto-Negotiation Next Page Transmit Register (Address 7)
Bit
Name
Description
Type 1
Default
7.15
Next Page
(NP)
1 = Additional next pages follow
0 = Last page
R/W
0
7.14
Reserved
Write as 0, ignore on read
RO
0
7.13
Message Page
(MP)
1 = Message page
0 = Unformatted page
R/W
1
7.12
Acknowledge 2
(ACK2)
1 = Complies with message
0 = Cannot comply with message
R/W
0
7.11
Toggle
(T)
1 = Previous value of the transmitted Link Code
Word equalled logic zero
0 = Previous value of the transmitted Link Code
Word equalled logic one
R/W
0
7.10:0
Message/Unformatted
Code Field
R/W
00000000
001
1. RO = Read Only. R/W = Read/Write
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WJLXT971ALE.A4SE001 DATACOM, ETHERNET TRANSCEIVER, PQFP64
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相关代理商/技术参数
参数描述
WJLXT971CA4 制造商:Intel 功能描述:
WJLXT972ALC.A4 功能描述:IC TRANS 3.3V ETHERNET 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:25 系列:- 类型:收发器 驱动器/接收器数:2/2 规程:RS232 电源电压:4.5 V ~ 5.5 V 安装类型:通孔 封装/外壳:16-DIP（0.300"，7.62mm） 供应商设备封装:16-PDIP 包装:管件
WJLXT972ALC.A4 S E001 制造商:Intel 功能描述:PHY 1-CH 10Mbps/100Mbps 64-Pin LQFP T/R
WJLXT972ALC.A4-857341 功能描述:TXRX ETH 10/100 SGL PORT 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422，RS485 电源电压:4.75 V ~ 5.25 V 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1402 (CN2011-ZH PDF)
WJLXT972ALC.A4-857345 功能描述:TXRX ETH 10/100 SGL PORT 64-LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器，接收器，收发器 系列:- 标准包装:1 系列:- 类型:线路收发器 驱动器/接收器数:5/3 规程:RS232 电源电压:3 V ~ 5.5 V 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC 包装:Digi-Reel® 产品目录页面:918 (CN2011-ZH PDF) 其它名称:296-25096-6
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