参数资料
| 型号： | XC2S400E-6FGG456C |
| 厂商： | Xilinx Inc |
| 文件页数： | 47/108页 |
| 文件大小： | 0K |
| 描述： | IC SPARTAN-IIE FPGA 400K 456FBGA |
| 产品变化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 标准包装： | 60 |
| 系列： | Spartan®-IIE |
| LAB/CLB数： | 2400 |
| 逻辑元件/单元数： | 10800 |
| RAM 位总计： | 163840 |
| 输入/输出数： | 329 |
| 门数： | 400000 |
| 电源电压： | 1.71 V ~ 1.89 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 85°C |
| 封装/外壳： | 456-BBGA |
| 供应商设备封装： | 456-FBGA |
| 其它名称： | 122-1327 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页当前第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页
DS077-3 (v3.0) August 9, 2013
43
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
DLL Timing Parameters
Because of the difficulty in directly measuring many internal
timing parameters, those parameters are derived from
benchmark timing patterns. The following guidelines reflect
worst-case values across the recommended operating con-
ditions.
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were deter-
mined through statistical measurement at the package pins
using a clock mirror configuration and matched drivers.
Figure 22, page 44, provides definitions for various parame-
ters in the table below.
Symbol
Description
FCLKIN
Speed Grade
Units
-7
-6
Min
Max
Min
Max
FCLKINHF
Input clock frequency (CLKDLLHF)
-
60
320
60
275
MHz
FCLKINLF
Input clock frequency (CLKDLL)
-
25
160
25
135
MHz
TDLLPW
Input clock pulse width
≥25 MHz
5.0
-
5.0
-
ns
≥50 MHz
3.0
-
3.0
-
ns
≥100 MHz
2.4
-
2.4
-
ns
≥150 MHz
2.0
-
2.0
-
ns
≥200 MHz
1.8
-
1.8
-
ns
≥250 MHz
1.5
-
1.5
-
ns
≥300 MHz
1.3
-
NA
-
Symbol
Description
FCLKIN
CLKDLLHF
CLKDLL
Units
Min
Max
Min
Max
TIPTOL
Input clock period tolerance
-
1.0
-
1.0
ns
TIJITCC
Input clock jitter tolerance (cycle-to-cycle)
-
±150
-
±300
ps
TLOCK
Time required for DLL to acquire lock(1)
> 60 MHz
-
20
-
20
μs
50-60 MHz
-
25
μs
40-50 MHz
-
50
μs
30-40 MHz
-
90
μs
25-30 MHz
-
120
μs
TOJITCC
Output jitter (cycle-to-cycle) for any DLL clock output(2)
-
±60
-
±60
ps
TPHIO
Phase offset between CLKIN and CLKO(3)
-
±100
-
±100
ps
TPHOO
Phase offset between clock outputs on the DLL(4)
-
±140
-
±140
ps
TPHIOM
Phase difference between CLKIN and CLKO(5)
-
±160
-
±160
ps
TPHOOM
Phase difference between clock outputs on the DLL(6)
-
±200
-
±200
ps
Notes:
1.
Commercial operating conditions. Add 30% for Industrial operating conditions.
2.
Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
3.
Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
4.
Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding output jitter and input clock jitter.
5.
Maximum Phase Difference between CLKIN and CLKO is the sum of output jitter and phase offset between CLKIN and CLKO, or
the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
6.
Maximum Phase Difference between Clock Outputs on the DLL is the sum of output jitter and phase offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
相关PDF资料 |
PDF描述 |
|---|---|
| XA6SLX100-2FGG484I | IC FPGA SPARTAN 6 484FGGBGA |
| 25LC640T-E/SN | IC EEPROM 64KBIT 2MHZ 8SOIC |
| SST25VF020B-80-4C-SAE-T | IC FLASH SER 2MB 80MHZ SPI 8SOIC |
| XC6SLX100-N3FGG484I | IC FPGA SPARTAN-6 484FPGA |
| SST25LF020A-33-4C-SAE | IC FLASH SER 2MB 33HZ SPI 8SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| XC2S400E-6FGG456I | 制造商:Xilinx 功能描述:FPGA SPARTAN-IIE 400K GATES 10800 CELLS 357MHZ 1.8V 456FBGA - Trays |
| XC2S400E-6FGG676C | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S400E-6FGG676I | 制造商:XILINX 制造商全称:XILINX 功能描述:Spartan-IIE FPGA |
| XC2S400E-6FT256C | 功能描述:IC SPARTAN-IIE FPGA 400K 256FTBG RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:Spartan®-IIE 产品变化通告:Step Intro and Pkg Change 11/March/2008 标准包装:1 系列:Virtex®-5 SXT LAB/CLB数:4080 逻辑元件/单元数:52224 RAM 位总计:4866048 输入/输出数:480 门数:- 电源电压:0.95 V ~ 1.05 V 安装类型:表面贴装 工作温度:-40°C ~ 100°C 封装/外壳:1136-BBGA，FCBGA 供应商设备封装:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XC2S400E-6FT256I | 制造商:Xilinx 功能描述:FPGA SPARTAN-IIE 400K GATES 10800 CELLS 357MHZ 1.8V 256FTBGA - Trays |
发布紧急采购，3分钟左右您将得到回复。