参数资料
型号: XC2S400E-6FGG456C
厂商: Xilinx Inc
文件页数: 52/108页
文件大小: 0K
描述: IC SPARTAN-IIE FPGA 400K 456FBGA
产品变化通告: FPGA Family Discontinuation 18/Apr/2011
标准包装: 60
系列: Spartan®-IIE
LAB/CLB数: 2400
逻辑元件/单元数: 10800
RAM 位总计: 163840
输入/输出数: 329
门数: 400000
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: 0°C ~ 85°C
封装/外壳: 456-BBGA
供应商设备封装: 456-FBGA
其它名称: 122-1327
48
DS077-3 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
Configuration Switching Characteristics
Symbol
Description
Speed Grade
Units
-7
-6
Max
TIO
IN input to OUT output
0
ns
TOFF
TRI input to OUT output high impedance
0.1
0.11
ns
TON
TRI input to valid data on OUT output
0.1
0.11
ns
Symbol
Description
Speed Grade
Units
-7
-6
Min
Max
Min
Max
Setup/Hold Times with Respect to TCK
TTAPTCK / TTCKTAP
TMS and TDI setup times and hold times
4.0 / 2.0
-
4.0 / 2.0
-
ns
Sequential Delays
TTCKTDO
Output delay from clock TCK to output TDO
-
11.0
-
11.0
ns
FTCK
TCK clock frequency
-
33
-
33
MHz
Notes:
1.
Before configuration can begin, VCCINT and VCCO Bank 2 must reach the recommended operating voltage.
Figure 23: Configuration Timing on Power-Up
DS001_12_102301
TPOR
TPL
TICCK
Valid
CCLK Output or Input
M0, M1, M2
(Required)
PROGRAM
INIT
VCC(1)
.
Symbol
Description
All Devices
Units
Min
Max
TPOR
Power-on reset
-
2
ms
TPL
Program latency
-
100
μs
TICCK
CCLK output delay (Master serial
mode only)
0.5
4
μs
TPROGRAM
Program pulse width
300
-
ns
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