参数资料
型号: ZL2004EVK1
厂商: Intersil
文件页数: 31/42页
文件大小: 0K
描述: KIT EVAL FOR ZL2004
标准包装: 1
系列: *
ZL2004
The tracking mode for all other devices can be set by
connecting a resistor from the SS pin to ground
according to Table 20. All of the ENABLE pins in the
tracking group must be connected together and driven
by a single logic source. CFG pin needs also to have
been set to the appropriate value to enable tracking
mode using pin-strap.
Tracking mode can also be configured via the
I 2 C/SMBus interface by using the TRACK_CONFIG
command.
Note that current sharing groups that are also
configured to track another voltage do not offer pre-
bias protection; a minimum load should therefore be
enforced to avoid the output voltage from being held
up by an outside force. Additionally, a device set up
for tracking must have both Alternate Ramp Control
and Precise Ramp-Up Delay disabled.
V IN
6.7 Voltage Margining
The ZL2004 offers a simple means to vary its output
higher or lower than its nominal voltage setting in
order to determine whether the load device is capable
of operating over its specified supply voltage range.
The MGN command is set by driving the MGN pin or
through the I 2 C/SMBus interface. The MGN pin is a
TTL-compatible input that is continuously monitored
and can be driven directly by a processor I/O pin or
other logic-level output.
The ZL2004 ’s output will be forced higher than its
nominal set point when the MGN command is set
HIGH, and the output will be forced lower than its
nominal set point when the MGN command is set
LOW. Default margin limits of V NOM ±5% are pre-
loaded in the factory, but the margin limits can be
modified through the I 2 C/SMBus interface to as high
as V NOM + 10% or as low as 0 V, where V NOM is the
nominal output voltage set point determined by the V0
ZL
PWMH
PWML
Driver
MOSFET
L1
V OUT
C1
and V1 pins. A safety feature prevents the user from
configuring the output voltage to exceed V NOM + 10%
under any conditions.
V TRK
V OUT
V TRK
V OUT
The margin limits and the MGN command can both be
set individually through the I 2 C/SMBus interface.
Additionally, the transition rate between the nominal
output voltage and either margin limit can be
configured through the I 2 C interface. Please refer to
Application Note AN33 for detailed instructions on
modifying the margining configurations.
Time
V OUT
Coincident
V TRK
V OUT
6.8 External Voltage Monitoring
The voltage monitoring (VMON) pin is available to
monitor the voltage supply for the external driver IC. If
the voltage falls below a predefined threshold value
(adjustable through a PMBus command), the device
will fault and stop sending PWM signals. A 1/16
Ratiometric
Time
external resistor divider is required to keep the
maximum voltage on this pin to less than 1.15 V.
Figure 18. Tracking Modes
31
FN6846.3
February 15, 2011
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