参数资料
型号: ZL2004EVK1
厂商: Intersil
文件页数: 8/42页
文件大小: 0K
描述: KIT EVAL FOR ZL2004
标准包装: 1
系列: *
ZL2004
3. Typical Application Circuit
The following application circuit represents a typical implementation of the ZL2004.
F.B. 1
V IN 12V
C IN
ENABLE
3 x 10 μF
POWER GOOD OUTPUT
DDC Bus 3
C V25
10 μF
4V
VBIAS
25 V
VDD
VIN
(To VR)
SGND
1 DGND
2 SYNC
3 SA0
4 SA1
5 ILIM
ZL2004
VDD
VR
PWMH
SGND
PWML
ISENA
24
23
22
21
20
19
PWMH
PWML
PWMH
ZL1505
GH
SW
Power Train
Module
V OUT
I 2 C/SMBus
(OPTIONAL) 2
6 SCL
7 SDA
8 SALRT
ISENB
NC
18
17
TEMP+
PWML
GL
TEMP-
GND
CS+
CS-
EPAD
RTN
100k
4.7 μF
6.3 V
C VR
SGND
6.65k
Notes:
1. Ferrite bead is optional for input noise suppression.
2. The I 2 C/SMBus requires pull-up resistors. Please refer to the I 2 C/SMBus specifications for more details.
3. The DDC bus requires a pull-up resistor. The resistance will vary based on the capacitive loading of the bus (and on the number of devices
connected). The 10 k
default value, assuming a maximum of 100 pF per device, provides the necessary 1 μs pull-up rise time. Please refer to
section 6.11 for more details.
Figure 3. 12 V to 1.8 V / 20 A Application Circuit
(4.5 V UVLO, 5 ms SS delay, 5 ms SS ramp)
8
FN6846.3
February 15, 2011
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