参数资料
型号: ZL2004EVK1
厂商: Intersil
文件页数: 7/42页
文件大小: 0K
描述: KIT EVAL FOR ZL2004
标准包装: 1
系列: *
ZL2004
Table 4. Pin Descriptions (continued)
Pin
Label
Type
1
Description
20
21
22
23
24
25
26
27
28
29
30
31
32
EPAD
PWML
SGND
PWMH
VR
VDD 3
V25
XTEMP
DDC
MGN
CFG
EN
SS
PG
SGND
O
PWR
O
PWR
PWR
PWR
I
I
I
M
I
I, M
O
PWR
PWM Gate low signal.
Connect to low impedance ground plane. Internal connection to SGND.
PWM Gate High signal.
Internal 5V reference used to power internal drivers.
Supply voltage.
Internal 2.5 V reference used to power internal circuitry.
External temperature sensor input. Connect to external 2N3904 (Base Emitter
junction).
Single wire DDC bus (Current sharing, inter device communication).
V OUT margin control.
Configuration pin. Used to control the switching phase offset, sequencing and
other management features.
Enable. Active signal enables PWM switching.
Soft start delay and ramp select. Sets the delay from when EN is asserted until the
output voltage starts to ramp and the ramp time.
Power good output.
Exposed thermal pad. Connect to low impedance ground plane. Internal
connection to SGND.
Notes:
1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins. (Refer to page 11).
2. The SYNC pin can be used as a logic pin, a clock input or a clock output.
3. V DD is measured internally and the value is used to modify the PWM loop gain.
7
FN6846.3
February 15, 2011
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