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| 型号： | ZL2004EVK1 |
| 厂商： | Intersil |
| 文件页数： | 4/42页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR ZL2004 |
| 标准包装： | 1 |
| 系列： | * |
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ZL2004
Table 3. Electrical Specifications
V DD = 12 V, T A = -40 C to 85 C unless otherwise noted. Typical values are at T A = 25 C. Boldface limits apply over
the operating temperature range, -40°C to +85°C.
Parameter
Conditions
Min
10
Typ
Max
10
Unit
Input and Supply Characteristics
I DD supply current at f SW = 200 kHz
I DD supply current at f SW = 1.4 MHz
I DDS shutdown current
VR reference output voltage
V25 reference output voltage
GH no load, GL no load,
MISC_CONFIG[7] = 1
EN = 0 V, No I 2 C/SMBus activity
V DD > 6 V, I VR < 50 mA
V R > 3 V, I V25 < 50 mA
–
–
–
4.5
2.25
16
25
6.5
5.2
2.5
30
50
8
5.7
2.75
mA
mA
mA
V
V
Output Characteristics
Output voltage adjustment range 1
Output voltage set-point resolution
Output voltage accuracy 3
VSEN input bias current
Current sense differential input
voltage (V OUT referenced)
Current sense input bias current
(V OUT referenced, V OUT <= 3.6V)
Soft start delay duration range
Soft start delay duration accuracy
Soft start ramp duration range
Soft start ramp duration accuracy
V IN > V OUT
Set using resistors
Set using I 2 C/SMBus
Includes line, load, temp
VSEN = 4 V
V ISENA - V ISENB
ISENA
ISENB
Set using SS pin or resistor
Set using I 2 C/SMBus
Turn-on delay (precise mode) 4,5
Turn-on delay (normal mode) 6
Turn-off delay 6
Set using SS pin or resistor
Set using I 2 C
0.6
–
–
-1
–
- 50
-1
- 100
2
0.002
–
–
–
2
0
–
–
10
±0.025
–
80
–
–
–
–
–
±0.25
-0.25/+4
-0.25/+4
–
–
100
3.6
–
–
1
150
50
1
100
20
500
–
–
–
20
200
–
V
mV
% FS 2
%
μA
mV
μA
μA
ms
s
ms
ms
ms
ms
ms
μs
Logic Input/Output Characteristics
Logic input bias current
MGN input bias current
Logic input low, V IL
Logic input OPEN (N/C)
Logic input high, V IH
Logic output low, V OL
Logic output high, V OH
EN,PG,SCL,SDA,SALRT pins
Multi-mode logic pins
I OL ≤ 4 mA
I OH ≥ -2 mA
- 10
-1
–
–
2.0
–
2.25
–
–
–
1.4
–
–
–
10
1
0.8
–
–
0.4
–
μA
mA
V
V
V
V
V
Notes:
1. Set point adjustment range does not include margin limits.
2. Percentage of Full Scale (FS) with temperature compensation applied.
3. V OUT set-point measured at the termination of the VSEN+ and VSEN- sense points.
4. The device requires approximately 2 ms following an enable signal and prior to ramping its output. The delay accuracy will vary by
±0.25 ms around the 2 ms minimum delay value.
5. Precise ramp timing mode is only valid when using EN pin to enable the device rather than PMBus enable.
6. The devices may require up to a 4 ms delay following an assertion of the enable signal (normal mode) or following the de-assertion
of the enable signal.
4
FN6846.3
February 15, 2011
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