参数资料
型号: ZL2004EVK1
厂商: Intersil
文件页数: 6/42页
文件大小: 0K
描述: KIT EVAL FOR ZL2004
标准包装: 1
系列: *
ZL2004
DGND
1
24
VDD
SYNC
SA0
SA1
ILIM
SCL
SDA
SALRT
2
3
4
5
6
7
8
32-Pin QFN
5 x 5 mm
Exposed Paddle
Connect to SGND
23
22
21
20
19
18
17
VR
PWMH
SGND
PWML
ISENA
ISENB
NC
2. Pin Descriptions
Figure 2. ZL2004 Pin Configurations (top view)
Table 4. Pin Descriptions
Pin
Label
Type
1
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
DGND
SYNC
SA0
SA1
ILIM
SCL
SDA
SALRT
FC
V0
V1
VMON
NC
VTRK
VSEN+
VSEN-
NC
ISENB
ISENA
6
PWR
I/O, M 2
I, M
I, M
I/O
I/O
O
I
I, M
I, M
I
I
I
I
I
Digital ground. Connect to low impedance ground plane.
Clock synchronization input. Used to set the frequency of the internal switch
clock, to sync to an external clock or to output internal clock.
Serial address select pins. Used to assign unique address for each individual
device or to enable certain management features.
Current limit select. Sets the overcurrent threshold voltage for ISENA, ISENB.
Serial clock. Connect to external host and/or to other ZL devices.
Serial data. Connect to external host and/or to other ZL devices.
Serial alert. Connect to external host if desired.
Loop compensation selection pin.
Output voltage selection pins. Used to set V OUT set-point and V OUT max.
External voltage monitoring (Can be used for external driver bias monitoring for
Power good).
No Connect.
Tracking sense input. Used to track an external voltage source.
Differential Output voltage sense feedback. Connect to positive output regulation
point.
Differential Output voltage sense feedback. Connect to negative output regulation
point.
No Connect.
Differential voltage input for current sensing.
Differential voltage input for current sensing. High voltage (DCR).
FN6846.3
February 15, 2011
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