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参数资料
| 型号： | ZL30108LDG1 |
| 厂商： | XILINX INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC32 |
| 封装： | 5 X 5 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-220, QFN-32 |
| 文件页数： | 35/57页 |
| 文件大小： | 691K |
| 代理商： | ZL30108LDG1 |
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ZL30108
Data Sheet
13
Zarlink Semiconductor Inc.
Digitally Controlled Oscillator (DCO) - the DCO receives the limited and filtered signal from the Loop Filter, and
based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is
dependent on the state of the ZL30108.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input
reference signal.
In the Automatic Holdover mode, the DCO is free running at a frequency equal to the frequency that the DCO was
generating in Normal Mode. The frequency in the Automatic Holdover mode is calculated from frequency samples
stored 26 ms to 52 ms before the ZL30108 entered the Automatic Holdover mode. This ensures that the coarse
frequency monitor and the single cycle monitor have time to disqualify a bad reference before it corrupts the
holdover frequency.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock-
window for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with
maximum network jitter and wander on the reference input. If the DPLL goes into the Automatic Holdover mode, the
LOCK pin will initially stay high for 0.1 s. If at that point the DPLL is still in the Automatic Holdover mode, the LOCK
pin will go low. In Freerun mode the LOCK pin will go low immediately.
4.5
Frequency Synthesizers
The output of the DCO is used by the frequency synthesizers to generate the output clocks and frame pulses which
are synchronized to one of the input references (REF0 or REF1).
The frequency synthesizer uses digital techniques to generate output clocks and advanced noise shaping
techniques to minimize the output jitter. The clock and frame pulse outputs have limited drive capability and should
be buffered when driving high capacitance loads.
4.6
State Machine
As shown in Figure 1, the state machine controls the TIE Corrector Circuit and the DPLL. The control of the
ZL30108 is based on the input MODE_SEL.
4.7
Master Clock
The ZL30108 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL30109 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30109_05 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with |
| ZL30109QDG | 制造商:Microsemi Corporation 功能描述: |
| ZL30109QDG1 | 制造商:Microsemi Corporation 功能描述:DS1/E1 System Synchronizer 64-Pin TQFP 制造商:Microsemi Corporation 功能描述:DS1/E1 SYS. SYNCH WITH 19.44MHZ 制造商:Microsemi Corporation 功能描述:DS1/E1 SYS SYNCHRONIZER 64TQFP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER DPLL 64TQFP 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER DPLL 64TQFP |
| ZL30110 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Telecom Rate Conversion DPLL |
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