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参数资料
| 型号： | ZL30108LDG1 |
| 厂商： | XILINX INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC32 |
| 封装： | 5 X 5 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-220, QFN-32 |
| 文件页数： | 48/57页 |
| 文件大小： | 691K |
| 代理商： | ZL30108LDG1 |
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ZL30108
Data Sheet
25
Zarlink Semiconductor Inc.
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
8.2
Performance Characteristics
* Supply voltage and operating temperature are as per Recommended Operating Conditions.
AC Electrical Characteristics* - OSCi 20 MHz Master Clock Input
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
Oscillator Tolerance
-20
+20
ppm
OOR_SEL=0
2
-32
+32
ppm
OOR_SEL=1
4
Duty cycle
40
60
%
5
Rise time
10
ns
6
Fall time
10
ns
Performance Characteristics* - Functional
Characteristics
Min.
Typ.
Max.
Units
Notes
1
Holdover accuracy
0.01
ppm
2
Holdover stability
NA
ppm
Determined by stability of
the 20 MHz Master Clock
oscillator
3
Capture range
-130
+130
ppm
The 20 MHz Master Clock
oscillator set at 0.ppm
4
Reference Out of Range
Threshold (including hysteresis)
-64
-83
+64
+83
ppm
The 20 MHz Master Clock
oscillator set at 0 ppm
and OOR_SEL=1
6-40
-52
+40
+52
ppm
The 20 MHz Master Clock
oscillator set at 0 ppm
and OOR_SEL=0
Lock Time
7
14 Hz Filter
1.5
s
input reference = 2 kHz,
±100 ppm frequency
offset, TIE_CLR=1
8
29 Hz Filter
1
s
input reference
≠ 2kHz,
±100 ppm frequency
offset, TIE_CLR=1
Output Phase Continuity (MTIE)
11
Reference switching
13
ns
12
Switching from Normal mode to
Automatic Holdover mode
0ns
13
Switching from Automatic
Holdover mode to Normal mode
13
ns
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