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参数资料
| 型号： | ZL30108LDG1 |
| 厂商： | XILINX INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, QCC32 |
| 封装： | 5 X 5 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-220, QFN-32 |
| 文件页数： | 39/57页 |
| 文件大小： | 691K |
| 代理商： | ZL30108LDG1 |
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ZL30108
Data Sheet
17
Zarlink Semiconductor Inc.
6.5
Holdover Accuracy
Holdover accuracy is defined as the absolute frequency accuracy of an output clock signal, when it is not locked to
an external reference signal, but is operating using storage techniques. For the ZL30108, the storage value is
determined while the device is in Normal Mode and locked to an external reference signal.
6.6
Capture Range
Also referred to as pull-in range. This is the input frequency range over which the PLL must be able to pull into
synchronization. The ZL30108 capture range is equal to
±130 ppm minus the accuracy of the master clock (OSCi).
For example, a +32 ppm master clock results in a capture range of +162 ppm on one side and -98 ppm on the other
side of frequency range.
6.7
Lock Range
This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock
range is equal to the capture range for the ZL30108.
6.8
Time Interval Error (TIE)
TIE is the time delay between a given timing signal and an ideal timing signal.
6.9
Maximum Time Interval Error (MTIE)
MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a
particular observation period.
6.10
Phase Continuity
Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a
particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency.
Phase continuity applies to the output of the PLL after a signal disturbance due to a reference switch or a mode
change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to
a steady state.
6.11
Phase Lock Time
This is the time it takes the PLL to phase lock to the input signal. Phase lock occurs when the input signal and
output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter).
Lock time is affected by many factors which include:
initial input to output phase difference
initial input to output frequency difference
PLL loop filter bandwidth
in-lock phase distance
The presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output
to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and
frequency.
Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.
For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock
time. See Section 8.2, “Performance Characteristics“ for Maximum Phase Lock Time.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ZL30109 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with 19.44 MHz Output |
| ZL30109_05 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:DS1/E1 System Synchronizer with |
| ZL30109QDG | 制造商:Microsemi Corporation 功能描述: |
| ZL30109QDG1 | 制造商:Microsemi Corporation 功能描述:DS1/E1 System Synchronizer 64-Pin TQFP 制造商:Microsemi Corporation 功能描述:DS1/E1 SYS. SYNCH WITH 19.44MHZ 制造商:Microsemi Corporation 功能描述:DS1/E1 SYS SYNCHRONIZER 64TQFP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER DPLL 64TQFP 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER DPLL 64TQFP |
| ZL30110 | 制造商:ZARLINK 制造商全称:Zarlink Semiconductor Inc 功能描述:Telecom Rate Conversion DPLL |
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