参数资料
型号: ZL30108LDG1
厂商: XILINX INC
元件分类: 数字传输电路
英文描述: ATM/SONET/SDH SUPPORT CIRCUIT, QCC32
封装: 5 X 5 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MO-220, QFN-32
文件页数: 4/57页
文件大小: 691K
代理商: ZL30108LDG1
ZL30108
Data Sheet
12
Zarlink Semiconductor Inc.
4.4
Digital Phase Lock Loop (DPLL)
The DPLL of the ZL30108 consists of a phase detector, an integrated on-chip loop filter, and a digitally controlled
oscillator as shown in Figure 8. The data path from the phase detector to the filter is tapped and routed to the lock
indicator that provides a lock indication which is output at the LOCK pin.
Figure 8 - DPLL Block Diagram
Phase Detector - the phase detector compares the virtual reference signal from the TIE corrector circuit with the
feedback signal and provides an error signal corresponding to the phase difference between the two. This error
signal is passed to the loop filter circuit.
Loop Filter - the loop filter is similar to a first order low pass filter with bandwidth of 29 Hz, suitable to provide timing
and synchronization for SONET/SDH network interface cards.
Detected REF Frequency
Loop Filter Bandwidth
2 kHz
14 Hz
8 kHz, 1.544 MHz,
2.048 MHz, 8.192 MHz,
16.384 MHz, 19.44 MHz
29 Hz
Table 1 - Loop Filter Bandwidth Settings
state select from
control state machine
feedback signal from
frequency select MUX
DPLL reference to
frequency synthesizer
virtual reference
from
TIE corrector circuit
loop filter
digitally
controlled
oscillator
phase
detector
lock
indicator
LOCK
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