![](http://datasheet.mmic.net.cn/160000/ZPSD813F3-12J_datasheet_10426290/ZPSD813F3-12J_35.png)
Preliminary
PSD813F Family
31
The
PSD813F
Functional
Blocks
(cont.)
Level 1
SRAM, I /O, or
Peripheral I /O
Level 2
EEPROM / Flash Boot
Memory
Highest Priority
Lowest Priority
Level 3
Flash Memory
Figure 7. Priority Level of Memory and I/O Components
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 8031 and compatible family of microcontrollers, which includes the 80C51, 80C151,
80C251, and 80C51XA, have separate address spaces for code memory (selected using
PSEN) and data memory (selected using RD). Any of the memories within the PSD813F
can reside in either space or both spaces. This is controlled through manipulation of the VM
register that resides in the PSD’s CSIOP space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, I may wish to have SRAM and Flash in Data Space at boot, and EEPROM in
Program Space at boot, and later swap EEPROM and Flash. This is easily done with
the VM register by using PSDsoft Configuration to configure it for boot up and having the
microcontroller change it when desired.
Table 13 describes the VM Register.
Bit 7
Bit 6* Bit 5*
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIO_EN
FL_Data EE_Data
FL_Code
EE_Code SRAM_Code
0 = disable
**
0 = RD
0 = PSEN
PIO mode
can’t
access
Flash
EEPROM/
Flash
EEPROM/
SRAM
Boot Flash
1= enable
**
1 = RD
1 = PSEN
PIO mode
access
Flash
EEPROM/
Flash
EEPROM/
SRAM
Boot Flash
Table 13. VM Register
NOTE: Bits 6-5 are not used.