PSD813F Family
Preliminary
100
-15
-20
Symbol
Parameter
Conditions
Min
Max
Min
Max
Unit
tLVLX
ALE or AS Pulse Width
28
30
tAVLX
Address Setup Time
(Note 1)
10
12
ns
tLXAX
Address Hold Time
(Note 1)
12
14
ns
tAVWL
Address Valid to Leading
Edge of WR
(Notes 1 and 3)
30
35
ns
t SLWL
CS Valid to Leading Edge of WR
(Note 3)
34
40
ns
t DVWH
WR Data Setup Time
(Note 3)
45
50
ns
t WHDX
WR Data Hold Time
(Note 3)
8
10
ns
t WLWH
WR Pulse Width
(Note 3)
48
53
ns
tWHAX
Trailing Edge of WR to Address Invalid
(Note 3)
0
ns
tWHPV
Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register
(Note 3)
45
50
ns
tWLMV
WR Valid to Port Output Valid Using
Micro
Cell Register Preset/Clear
(Notes 3 and 4)
90
100
ns
tWHQV1
Byte Programming Operation
Also including
pre-programming time
14
s
tWHQV2
Sector Erase Operation
Note 100% tested
2.2
sec
tQ7VQV
Q7 Valid to Output Valid (Data Polling)
70
75
ns
tVCS
VCC Setup Time
VCC High to First Flash WR Low
45
50
s
tDVMV
Data Valid to Port Output Valid
Using Micro
Cell Register Preset/Clear
(Notes 3 and 5)
90
100
ns
tAVPV
Address Input Valid to Address
(Note 2)
48
55
ns
Output Delay
Write, Erase and Program Timing (3.0 V to 3.6 V Versions)
NOTES: 1. Any input used to select an internal PSD813F function.
2. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port.
3. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active write signal.
5. Assuming write is active before data becomes valid.
Microcontroller Interface – ZPSD813FV AC/DC Parameters
(3.0 V to 3.6 V Versions)