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| 型号： | 78Q8430-100IGT/F |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 22/88页 |
| 文件大小： | 0K |
| 描述： | IC LAN MEDIA ACCESS CTLR 100LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 90 |
| 控制器类型： | 以太网控制器，MAC/PHY |
| 电源电压： | 3.3V |
| 电流 - 电源： | 230mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
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DS_8430_001
78Q8430 Data Sheet
Rev. 1.2
29
If small packets are a problem, then the Mode setting of 10b can be used. In this mode, the QDR bit for
the QUE is set only when there is an EOF in the QUE, or in other words, the QUE contains at least one
entire frame. In this mode, TX FIFO under-runs are not possible since the QUE will not begin to transmit
until it contains the entire frame. The draw-back to this mode is with very large frames. If a frame is too
large to fit into the QUE all at one time then it will never begin transmitting and the QUE will be stalled.
If both small and large packets are to be handled then a Mode setting of 11b should be used. In this
mode, the QDR bit for the QUE is set anytime there is an EOF in the QUE or the number of BLOCKs in
the QUE is above the threshold. In this way, large packets can preload a fixed number of BLOCKs while
small packets are guaranteed to transmit.
To facilitate the handling of very large packets by a fast host, an interrupt that is tied to the QSR
Threshold is provided. To make use of this, the host sets the Threshold field based on the interrupt
latency. The host then preloads the QUE with some number of BLOCKs. As soon as the total number of
blocks left in the QUE falls below the Threshold, an interrupt is generated. In response to the interrupt
the host writes more data to the QUE to put the number back above the threshold. The host can then go
on to other tasks until the next interrupt. This cycle is repeated until the frame is completed.
6.3.3
DMA Slave Mode Access
Reading or writing large amounts of data into and out of a single QUE involves accessing the same RDR
or TDR register repeatedly. A DMA Slave Mode is implemented to facilitate this activity and reduce
overhead on the host side. While in DMA Slave Mode, the address bus on the host interface is ignored
and all access is assumed to be to the programmed address until DMA mode is terminated. In this way
the host can use a DMA engine or block transfer facility to write or read QUE data without regard to the
addresses generated.
DMA Slave Mode is controlled by the DMA Register (DMA) at address 0x100.
To read data from a QUE using DMA Slave Mode, the host writes the address of the RDR for the desired
QUE into bits nine through zero and sets bit 17, the Read Mode bit, in the DMA register at address
0x100. The host then starts the DMA transfer and all read access to the host interface will go to the
programmed RDR address. When the DMA transfer is complete, the DMA Mode is terminated by writing
a zero to bit 17 of the DMA Register (DMA).
To write data to a QUE using DMA Slave Mode, the host writes the address of the TDR for the desired
QUE into bits nine through zero and sets bit 16, the Write Mode bit, in the DMA Register. The host then
starts the DMA transfer and all write access to the host interface will go to the programmed TDR address.
When the DMA transfer is complete, reading the cleared Write Mode bit from the DMA Register
terminates the DMA Mode.
DMA Slave Mode does not have any effect on other operations of the interface such that, for example,
the ENDIAN settings, STDR settings, etc. are all in effect during a DMA Mode transfer. During a DMA
mode transfer, the actual register address of the host bus access is ignored. This means that using DMA
Slave Mode to transfer data out of order is not supported. Data words must always be written to a
transmit QUE in the desired transmit order and are always read from a receive QUE in received order.
6.4
Snoop Mode Access
The Snoop Interface provides a means by which QUE data can be inspected and modified in situ, leaving
the state of the QUE unchanged. The Snoop Interface works by presenting the contents of a specific
BLOCK of QUE memory at the SNOOP address space 0x300-0x3FF. The Snoop Control Register
(SNCR) is used to set which BLOCK of QUE memory is mapped into the SNOOP address space.
For example, an application that wishes to inspect or modify the contents of the first frame in the receive
pointer to the FIRST BLOCK in QUE0 is then written to the SNCR register. Now that the SNCR Register
has programmed the SNOOP interface to point to the FIRST BLOCK for QUE0, accessing registers in the
address space from 0x300 to 0x3FF will be directly accessing the data for the first frame contained in
QUE0.
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