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| 型号： | 78Q8430-100IGT/F |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 39/88页 |
| 文件大小： | 0K |
| 描述： | IC LAN MEDIA ACCESS CTLR 100LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 90 |
| 控制器类型： | 以太网控制器，MAC/PHY |
| 电源电压： | 3.3V |
| 电流 - 电源： | 230mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 托盘 |
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78Q8430 Data Sheet
DS_8430_001
44
Rev. 1.2
6.8
Timers
The Timers block implements several timers used within the system. Watermarking for main memory is
also handled in this block as it relates to the PAUSE operation.
6.8.1
PAUSE Timer
The PAUSE timer is used to implement the MAC Control PAUSE operation described in Annex 31B of
IEEE STD 802.3-2002. It consists of a 16-bit counter that determines the duration of the pause state.
The host can also trigger a local pause state via the Start Pause bit of the PDCR.
6.8.2
HNR Timer
The Host Not Responding timer is used to notify remote nodes that have requested a Wake-On-LAN that
the local host is not responding to the request. The host, knowing about how long it should take to wake,
sets the value for how long to wait after a wake request for the host to clear the interrupt before a timeout
triggers the transmission of a Host Not Responding packet. This value is set in the Host Not Responding
The host can determine the wake status by reading the Power Management Control and Status Register
(PMCSR). The default state is clear.
The HNR counter is decremented on every system clock that it has a non-zero value.
6.8.3
Interrupt Delay Timer
The Interrupt Delay Timer is used to delay the received data interrupt to the host. The host determines
how long the delay should be by writing a value to the Interrupt Delay Count Register (IDCR).
As noted above, the interrupt timer is using MAC receive byte times as its unit of time. The value written
to the IDCR can therefore be thought of as the maximum number of bytes that could possibly be received
between the time the first data was added to the QUE and when the received data interrupt is actually
triggered.
6.9
EEPROM Controller
The PROM controller provides logic for reading and writing an optional external EEPROM or ROM device.
The external devices supported are the MicroChip 93LC46B and the National NM93C46. Timing
compatible devices, smaller devices and read-only equivalent devices are also supported.
The basic sequences of events in accessing an external EEPROM or serial ROM are:
System software reads the busy bit to ensure the EEPROM controller is not busy.
On a write, the data should be written into the data register before setting the control register.
Software writes the address and the read/write flag and sets the busy bit.
The controller completes the operation and clears the busy bit.
On a read, when system software detects the busy bit is cleared, it can read the data register.
6.10 Ethernet MAC
The MAC consists of a transmit block, a receive block, a control register, a flow control block and a serial
controller for station management communications to the PHY and the optional external EEPROM/ROM.
The MAC also has a loop back circuit.
6.10.1 MAC Transmit Block
The MAC transmit block moves the outgoing data from the MAC transmit FIFO, encapsulates it and
passes it on to the MII interface logic in the PHY. The transmit block has circuits for generating preamble
and jam bytes, pad bytes, the CRC value and error extension. The transmit block also has a timer for the
back-off delay after a collision and a timer for the inter-packet gap after transmission.
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