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参数资料
| 型号： | 935263912557 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1 MM HEIGHT, PLASTIC, SOT-386-1, TQFP-100 |
| 文件页数： | 26/56页 |
| 文件大小： | 277K |
| 代理商： | 935263912557 |
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Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
32
13.1.7
Global Interrupt Status and TX Control (GLOBCSR) – Base Address: 0x018
This register is the top level interrupt status register. If the external interrupt line is set, this register will indicate which major portion of the AV
Link generated the interrupt. There is no interrupt acknowledge required at this level. These bits auto clear when the interrupts in the
appropriate section of the device are cleared or disabled. Control of the AV transceiver is also provided by this register.
Bits 0 to 3 are used to identify which internal modules are currently generating an interrupt. After identifying the module, the appropriate register
in that module must be read to determine the exact cause of the interrupt.
NOTES
1. There can be more than one interrupt source active at the same time.
2. The HIF INT_N signal (pin 28) remains active as long as there is at least one more enabled active interrupt status bit.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ASYTX/RX
ITXINT
IRXINT
LNKPHYINT
31 30
EASYTX/RX
EITXINT
EIRXINT
ELNKPHYINT
DIRA
V1
ENOUT
A
V
2
ENOUT
A
V
1
SV00857
Reset Value 0x00010000
Bit 18:
R/W
Enable output AVPORT2: A ‘1’ enables AVPORT2 as an output. A ‘0’ sets the 3-State condition on the port. In
3-State condition the port may be used as an input or unused output according to the state of DIRAV1 (bit 16).
Bit 17:
R/W
Enable output AVPORT1: A ‘1’ enables AVPORT1 as an output. A ‘0’ sets the 3-State condition on the port. In
3-State condition the port may be used as an input or unused output according to the state of DIRAV1 (bit 16).
Bit 16:
R/W
Direction of AVPORT1 (DIRAV1): A ‘1’ enables AVPORT1 as a transmitter, thus AVPORT1 pins are inputs. A ‘0’
configures AVPORT1 as a receiver, AVPORT1 pins are outputs in this configuration. The configuration of AVPORT2
pins is opposite of AVPORT1 pins. When AVPORT1 is set to transmit, AVPORT2 receives and vice versa.
Bit 11:
R/W
Enables generation of external interrupt by asynchronous transmitter and receiver module (ASYTX/RX, bit 3) when
set (1). Disables such interrupts when clear (0) (regardless of ASYINTE contents).
Bit 10:
R/W
Enables generation of external interrupt by the isochronous transmitter module (ITXINT, bit 2) when set (1).
Disables such interrupts when clear (0) (regardless of ITXINTE contents).
Bit 9:
R/W
Enables generation of external interrupt by the isochronous receiver module (IRXINT, bit 1) when set (1).
Disables such interrupts when clear (0) (regardless of IRXINTE contents).
Bit 8:
R/W
Enables generation of external interrupt by general link/phy module (LKPHYINT, bit 0) when set (1). Disables such
interrupts when clear (0) (regardless of LNKPHYINTE contents).
Bit 3:
R
Asynchronous Transmitter/Receiver Interrupt (ASYITX/RX): Interrupt source is in the Asynchronous Transmitter/
Receiver Interrupt Acknowledge/Source register.
Bit 2:
R
AV Transmitter Interrupt (ITXINT): Interrupt source is in the AV Transmitter Interrupt Acknowledge/Source register.
Bit 1:
R
AV Receiver Interrupt (IRXINT): Interrupt source is in the AV Receiver Interrupt Acknowledge/Source register.
Bit 0:
R
Link-Phy Interrupt (LNKPHYINT): Interrupt source is in the Link Phy Interrupt Acknowledge register.
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