- 您现在的位置：买卖IC网 > PDF目录24812 > 935263912557 (NXP SEMICONDUCTORS) 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 PDF资料下载
参数资料
| 型号： | 935263912557 |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 封装： | 14 X 14 MM, 1 MM HEIGHT, PLASTIC, SOT-386-1, TQFP-100 |
| 文件页数： | 38/56页 |
| 文件大小： | 277K |
| 代理商： | 935263912557 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页当前第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页
Philips Semiconductors
Preliminary specification
PDI1394L21
1394 full duplex AV link layer controller
2000 Jun 06
43
13.3.7
Asynchronous Receive Request (RREQ) – Base Address: 0x098
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RREQ
SV00297
3130
Reset Value 0x00000000
Bit 31..0:
R
RREQ:Quadlet of packet from receiver request queue (transfer register).
Reading this register will clear the RREQQQAV flag until the next received quadlet is available for reading.
13.3.8
Asynchronous Receive Response (RRSP) – Base Address: 0x09C
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RRSP
SV00298
31 30
Reset Value 0x00000000
Bit 31..0:
R
RRSP:Quadlet of packet from receiver response queue (transfer register).
Reading this register will clear the RRSPQQAV flag until the next received quadlet is available for reading.
13.3.9
Asynchronous RX/TX Interrupt Acknowledge (ASYINTACK) – Base Address: 0x0A0
SV01077
29 28
27 26 25 24 23
22 21 20 19 18
17 16
15 14 13
12 11 10
9
8
7
6
5
4
3
2
1
0
TIMEOUT
RCVDRSP
RRSPQFULL
RREQQFULL
RREQQQA
V
RRSPQRDERR
RREQQRDERR
RRSPQQA
V
SIDQA
V
RREQQLASTQ
TRSPQFULL
RRSPQLASTQ
TREQQWRERR
TRSPQWR
TRSPQWRERR
TREQQFULL
TREQQWR
31 30
Reset Value 0x00000C00
Bit 31..17:
R/W
Unused bits read ‘0’
Bit 16:
R/W
RRSPQFULL: Receiver response queue did become full. Write a “1” to this bit to reset the interrupt.
Bit 15:
R/W
RREQQFULL: Receiver request queue did become full. Write a “1” to this bit to reset the interrupt.
Bit 14:
R/W
SIDQAV: Current quadlet in RREQ is self ID data. This bit is set only after a bus reset, not after reception of PHY
packets other than self IDs. This interrupt automatically resets when the quadlet is read.
Bit 13:
R/W
RRSPQLASTQ: Current quadlet in RRSP is last quadlet of packet. This interrupt automatically resets when the
quadlet is read.
Bit 12:
R/W
RREQQLASTQ: Current quadlet in RREQ is last quadlet of packet. This interrupt automatically resets when the
quadlet is read.
Bit 11:
R/W
RRSPQRDERR: Receiver response queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access. Write a “1” to this bit to reset the interrupt.
Bit 10:
R/W
RREQQRDERR: Receiver request queue read error (transfer error) or bus reset occurred.
When set (1), this queue is blocked for read access. Write a “1” to this bit to reset the interrupt.
Bit 9:
R/W
RRSPQQAV: Receiver response queue quadlet available (in RRSP). This interrupt automatically resets when the
quadlet is read.
Bit 8:
R/W
RREQQQAV: Receiver request queue quadlet available (in RREQ). This interrupt automatically resets when the
quadlet is read.
Bit 7:
R/W
TIMEOUT: Split transaction response timeout. Write a “1” to this bit to reset the interrupt.
Bit 6:
R/W
RCVDRSP: Solicited response received (within timeout interval). Write a “1” to this bit to reset the interrupt.
Bit 5:
R/W
TRSPQFULL: Transmitter response queue did become full. Write a “1” to this bit to reset the interrupt.
Bit 4:
R/W
TREQQFULL: Transmitter request queue did become full. Write a “1” to this bit to reset the interrupt.
Bit 3:
R/W
TRSPQWRERR: Transmitter response queue write error (transfer error). Write a “1” to this bit to reset the interrupt.
Bit 2:
R/W
TREQQWRERR: Transmitter request queue write error (transfer error). Write a “1” to this bit to reset the interrupt.
Bit 1:
R/W
TRSPQWR: Transmitter response queue written (transfer register emptied). Write a “1” to this bit to reset the interrupt.
相关PDF资料 |
PDF描述 |
|---|---|
| 935263912551 | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP100 |
| 08-1101-00 | DREHSCHALTER 1POL 12STELLUNGEN |
| 08-1260-00 | ************GESTRICHEN************ |
| 08-1341-00 | DREHSCHALTER 3POL 4STELLUNGEN |
| 08-2101-00 | DREHSCHALTER 2POL 12STELLUNGEN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 935264217557 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935267356112 | 制造商:NXP Semiconductors 功能描述:IC TEA1507PN |
| 935268081112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY IC |
| 935268721125 | 制造商:NXP Semiconductors 功能描述:Buffer/Line Driver 1-CH Non-Inverting 3-ST CMOS 5-Pin TSSOP T/R |
| 935269304128 | 制造商:ST-Ericsson 功能描述:IC AUDIO CODEC W/TCH SCRN 48LQFP |
发布紧急采购，3分钟左右您将得到回复。