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参数资料
| 型号： | AD6634 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 基带处理器 |
| 英文描述： | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| 中文描述： | 80 MSPS的双通道的WCDMA接收信号处理器（RSP） |
| 文件页数： | 23/52页 |
| 文件大小： | 925K |
| 代理商： | AD6634 |
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REV. 0
AD6634
–23–
The NCO frequency value in registers 0x85 and 0x86 is interpreted
as a 32-bit unsigned integer. The NCO frequency is calculated
using the equation below.
NCO FREQ
_
MOD
f
CLK
CHANNEL
=
×
2
32
where,
NCO_FREQ
is the 32-bit integer (registers 0x85 and 0x86),
f
CHANNEL
is the desired channel frequency, and
CLK
is the AD6634
master clock rate or input data rate depending on the Input
Enable mode used. See Input Enable Control section.
NCO Frequency Hold-Off Register
When the NCO Frequency registers are written, data is actually
passed to a shadow register. Data may be moved to the main
registers by one of two methods: when the channel comes out of
sleep mode or when a SYNC Hop occurs. In either event a
counter can be loaded with NCO Frequency Hold-Off register
value. The 16-bit unsigned integer counter (0x84) starts count-
ing down clocked by the master clock and when it reaches zero,
the new frequency value in the shadow register is written to the
NCO Frequency register. The NCO could also be set up to SYNC
immediately, in which case the Frequency Hold-off counter is
bypassed and new frequency values are updated immediately.
Phase Offset
The phase offset register (0x87) adds an offset to the phase
accumulator of the NCO. This is a 16-bit register and is inter-
preted as a 16-bit unsigned integer. A 0x0000 in this register
corresponds to a 0 Radian offset and a 0xFFFF corresponds to
an offset of 2 (1-1/(2
16
)) Radians. This register allows multiple
NCOs to be synchronized to produce sine waves with a known
and steady phase difference.
NCO Control Register
The NCO control register located at 0x88 is used to configure
the features of the NCO. These are controlled on a per-channel
basis, and are described below.
Bypass
The NCO in the front end of the AD6634 can be bypassed.
Bypass mode is enabled by setting Bit 0 of 0x88 high. When it is
bypassed, down conversion is not performed and the AD6634
channel functions simply as a real filter on complex data. This is
useful for baseband sampling applications where the A input is
connected to the I signal path within the filter and the B input is
connected to the Q signal path. This may be desired if the digi-
tized signal has already been converted to baseband in prior
analog stages or by other digital preprocessing.
Phase Dither
The AD6634 provides a phase dither option for improving the
spurious performance of the NCO. Phase dither is enabled by
setting Bit 1. When phase dither is enabled by setting this bit
high, spurs due to phase truncation in the NCO are randomized.
The energy from these spurs is spread into the noise floor and
spurious-free dynamic range is increased at the expense of very
slight decreases in the SNR. The choice of whether phase
dither is used in a system will ultimately be decided by the
system goals. It should be employed if lower spurs are desired
at the expense of a slightly raised noise floor. If a low noise floor
is desired, and the higher spurs can be tolerated or filtered by
subsequent stages, phase dither is not needed.
Amplitude Dither
Amplitude dither can also be used to improve spurious performance
of the NCO. Amplitude dither is enabled by setting Bit 2.
Amplitude dither improves performance by randomizing the
amplitude quantization errors within the angular to Cartesian
conversion of the NCO. This option may reduce spurs at the
expense of a slightly raised noise floor. Amplitude dither and
phase dither can be used together, separately, or not at all.
Clear Phase Accumulator on HOP
When Bit 3 is set, the NCO phase accumulator is cleared prior
to a frequency hop. This ensures a consistent phase of the NCO
on each hop. The NCO phase offset is unaffected by this setting
and is still in effect. If phase continuous hopping is desired, this
bit should be cleared and the last phase in the NCO phase register
will be the initiating point for the new frequency.
Input Enable Control
There are four different modes of operation for the input enable.
Each of the high speed input ports includes an IEN line. Any of
the four filter channels can be programmed to take data from either
of the two A or B input ports. (See WB Input Select section.)
Along with data is the IEN(A,B) signal. Each filter channel can be
configured to process the IEN signal in one of four modes. Three
of the modes are associated with when data is processed based
on a time division multiplexed data stream. The fourth mode is
used in applications that employ time division duplex such as
radar, sonar, ultrasound, and communications that involve TDD.
Mode 00: Blank on IEN Low
In this mode, data is blanked while the IEN line is low. During
the period of time when the IEN line is high, new data is strobed
on each rising edge of the input clock. When the IEN line is
lowered, input data is replaced with zero values. During this
period, the NCO continues to run such that when the IEN line
is raised again, the NCO value will be at the value it would have
been otherwise had the IEN line never been lowered. This mode
has the effect of blanking the digital inputs when the IEN line is
lowered. Back end processing (rCIC2, CIC5, and RCF) continues
while the IEN line is high. This mode is useful for time division
multiplexed applications.
Mode 01: Clock on IEN High
In this mode, data is clocked into the chip while the IEN line is
high. During the period of time when the IEN line is high, new
data is strobed on each rising edge of the input clock. When
the IEN line is lowered, input data is no longer latched into
the channel. Additionally, NCO advances are halted. However,
back end processing (rCIC2, CIC5, and RCF) continues during
this period. The primary use for this mode is to allow for a clock
that is faster than the input sample data rate to allow more filter
taps to be computed than would otherwise be possible. In Fig-
ure 30, input data is strobed only during the period of time that
IEN is high despite the fact that the CLK continues to run at a
rate four times faster than the data.
n+1
n
IN[13:0]
E[2:0]
CLK
IEN
t
SI
t
HI
Figure 30. Fractional Rate Input Timing (4x CLK)
in Mode 01
相关PDF资料 |
PDF描述 |
|---|---|
| AD6634BBC | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6634PCB | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6635BB | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6636 | 150 MSPS Wideband Digital Down-Converter (DDC) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6634BBC | 功能描述:IC RSP 80MSPS DUAL 196-CSPBGA RoHS:否 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BBCZ | 功能描述:IC RSP 80MSPS DUAL 196CSPBGA RoHS:是 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BC/PCB | 制造商:Analog Devices 功能描述:WCDMA RECEIVE SGNL PROCESSOR - Bulk |
| AD6634PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
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