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| 型号： | AD6634 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 基带处理器 |
| 英文描述： | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| 中文描述： | 80 MSPS的双通道的WCDMA接收信号处理器（RSP） |
| 文件页数： | 46/52页 |
| 文件大小： | 925K |
| 代理商： | AD6634 |
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REV. 0
–46–
AD6634
set between 1 and 4 with bit representation 00 meaning one
sample and bit representation 11 meaning four samples.
0x11 AGC A Update Decimation
This 12-bit register sets the AGC decimation ratio from 1 to 4096.
An appropriate scaling factor should be set to avoid loss of bits.
0x12 AGC B Control Register
This 8-bit register controls features of the AGC A. The bits are
defined below:
Bits 7–5 define the output word length of the AGC. The output
word can be 4–8, 10, 12, or 16 bits wide. The control register
bit representation to obtain different output word lengths is
given in the Memory Map table.
Bit 4 of this register sets the mode of operation for the AGC.
When this bit is 0, the AGC tracks to maintain the output signal
level and when this bit is 1, the AGC tracks to maintain a con-
stant clipping error. Consult the AGC section for more details
about these modes.
Bits 3–1 are used to configure the synchronization of the AGC.
The CIC decimator filter in the AGC can be synchronized to an
external sync signal to output an update sample for the AGC
error calculation and filtering. This way the AGC gain changes
can be synchronized to an external block like a Rake receiver.
Whenever an external sync signal is received, the hold-off counter
at 0x0B is loaded and begins to count down. When the counter
reaches one, the CIC filter dumps an update sample and starts
working towards a new update sample. The AGC can be initial-
ized on each SYNC or only on the first SYNC.
Bit 3 is used to issue a command to the AGC to SYNC immedi-
ately. If this bit is set, the CIC filter will update the AGC with a
new sample immediately and start operating towards the next
update sample. The AGC can be synchronized by the microport
control interface using this method.
Bit 2 is used to determine whether the AGC should initialize on
a SYNC or not. When this bit is set, the CIC filter is cleared and
new values for CIC decimation, number of averaging samples,
CIC scale, Signal gain G
S
, gain K and pole parameter P are
loaded. When Bit 2 = 0, the above-mentioned parameters are
not updated and the CIC filter is not cleared. In both cases, an
AGC update sample is output from the CIC filter and the
decimator starts operating towards the next output sample
whenever a SYNC occurs.
Bit 1 is used to ignore repetitive synchronization signals. In some
applications, the synchronization signal may occur periodically.
If this bit is clear, each synchronization request will resynchronize
the AGC. If this bit is set, only the first occurrence will cause the
AGC to synchronize and will update AGC gain values periodi-
cally depending on the decimation factor of the AGC CIC filter.
Bit 0 is used to bypass the AGC section, when it is set. The
23-bit representation from interpolating half-band filters is still
reduced to a lower bit width representation as set by Bits 7–5 of
the AGC A Control Register. A truncation at the output of the
AGC accomplishes this task.
0x13 AGC B Hold-Off Counter
The AGC A Hold-Off counter is loaded with the value written
to this address when either a Soft_SYNC or Pin_SYNC comes
into the channel. The counter begins counting down so when it
reaches one, a SYNC is given to AGC A. This SYNC may or may
not initialize the AGC, as defined by the control word. The AGC
loop is updated with a new sample from the CIC filter whenever a
SYNC occurs. If this register is written to one, the AGC will be
updated immediately when the SYNC occurs. If this register
is written to a zero the AGC cannot be synchronized.
0x14 AGC B Desired Level
This 8-bit register contains the desired output power level or
desired clipping level, depending on the mode of operation.
This desired Request R level can be set in dB from 0 to –23.99 in
steps of 0.094 dB. 8-bit binary floating-point representation is
used with 2-bit exponent followed by 6-bit mantissa. Mantissa is
in steps of 0.094 dB and exponent in 6.02 dB steps. For example,
10’100101 represents 2
6.02 + 37
0.094 = 15.518 dB.
0x15 AGC B Signal Gain
This register is used to set the initial value for a Signal Gain used
in the gain multiplier. This 12-bit value sets the initial signal
gain between 0 and 96.296 dB in steps of 0.024 dB. 12-bit
binary floating-point representation is used with 4-bit exponent
followed by 8-bit mantissa. For example, 0111’10001001 is
equivalent to 7
6.02 + 137
0.024 = 45.428 dB.
0x16 AGC B Loop Gain
This 8-bit register is used to define the open loop gain, K. Its
value can be set from 0 to 0.996 in steps of 0.0039. This value of K
is updated in the AGC loop each time the AGC is initialized.
0x17 AGC B Pole Location
This 8-bit register is used to define the open loop filter pole
location P. Its value can be set from 0 to 0.996 in steps of 0.0039.
This value of P is updated in the AGC loop each time the AGC is
initialized. This open loop pole location will directly impact the
closed loop pole locations as explained in the AGC section.
0x18 AGC B Average Samples
This 6-bit register contains the scale used for the CIC filter and
the number of power samples to be averaged before being fed to
the CIC filter.
Bits 5–2 define the scale used for the CIC filter.
Bits 1–0 define the number of samples to be averaged before
they are sent to the CIC decimating filter. This number can be
set between 1 and 4 with bit representation 00 meaning one
sample and bit representation 11 meaning four samples.
0x19 AGC B Update Decimation
This 12-bit register sets the AGC decimation ratio from 1 to 4096.
An appropriate scaling factor should be set to avoid loss of bits.
0x1A Parallel Port Control A
Data is output through either a parallel port interface or a link port
interface. When 0x1B Bit 7 = 0, the use of link port A is disabled
and the use of parallel port A is enabled. The parallel port pro-
vides different data modes for interfacing with DSPs or FPGAs.
Bit 0 selects which data is output on parallel port A. When
Bit 0 = 0, parallel port A outputs data from the RCF according
to the format specified by Bits 1 through 4. When Bit 0 = 1,
parallel port A outputs the data from the AGCs according to the
format specified by Bits 1 and 2.
In AGC mode, Bit 0 = 1, Bit 1 determines if parallel port A is
able to output data from AGC A, and Bit 2 determines if parallel
port A is able to output data from AGC B. The order of output
depends on the rate of triggers from each AGC, which in turn is
determined by the decimation rate of the channels feeding it. In
channel mode, Bit 0 = 0 and Bits 1 through 4 determine which
combination of the four processing channels is output. The
output order depends on the rate of triggers received from each
相关PDF资料 |
PDF描述 |
|---|---|
| AD6634BBC | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6634PCB | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6635BB | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6636 | 150 MSPS Wideband Digital Down-Converter (DDC) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6634BBC | 功能描述:IC RSP 80MSPS DUAL 196-CSPBGA RoHS:否 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BBCZ | 功能描述:IC RSP 80MSPS DUAL 196CSPBGA RoHS:是 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BC/PCB | 制造商:Analog Devices 功能描述:WCDMA RECEIVE SGNL PROCESSOR - Bulk |
| AD6634PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
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