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参数资料
| 型号： | AD6634 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 基带处理器 |
| 英文描述： | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| 中文描述： | 80 MSPS的双通道的WCDMA接收信号处理器（RSP） |
| 文件页数： | 27/52页 |
| 文件大小： | 925K |
| 代理商： | AD6634 |
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REV. 0
AD6634
–27–
RAM COEFFICIENT FILTER
The final signal processing stage is a sum-of-products decimat-
ing filter with programmable coefficients. A simplified block
diagram is shown in Figure 31. The data memories I-RAM and
Q-RAM store the 160 most recent complex samples from the
previous filter stage with 20-bit resolution. The coefficient
memory, CMEM, stores up to 256 coefficients with 20-bit
resolution. On every CLK cycle, one tap for I and one tap for Q
are calculated using the same coefficients. The RCF output
consists of 24-bit data bits.
160 20B
I-RAM
I IN
I OUT
256 20B
C-RAM
160 20B
Q-RAM
Q IN
Q OUT
Figure 31. RAM Coefficient Filter Block Diagram
RCF Decimation Register
Each RCF channel can be used to decimate the data rate. The
decimation register is an 8-bit register and can decimate from
1 to 256. The RCF decimation is stored in 0xA0 in the form of
M
RCF
–1. The input rate to the RCF is f
SAMP5
.
RCF Decimation Phase
The RCF decimation phase can be used to synchronize multiple
filters within a chip. This is useful when using multiple channels
within the AD6634 to implement the polyphase filter, allowing the
resources of several filters to be paralleled. In such an application,
two RCF filters would be processing the same data from the CIC5.
However, each filter will be delayed by one-half the decimation
rate, thus creating a 180 degree phase difference between the two
halves. The AD6634 filter channel uses the value stored in this
register to preload the RCF counter. Therefore, instead of starting
from 0, the counter is loaded with this value, thus creating an
offset in the processing that should be equivalent to the required
processing delay. This data is stored in 0xA1 as an 8-bit number.
RCF Filter Length
The maximum number of taps this filter can calculate,
N
taps
, is
given by the equation below. The value N
taps
–1 is written to the
channel register within the AD6634 at address 0xA2.
N
f
M
f
taps
CLK
RCF
SAMP
≤
×
min
5
160
,
The RCF coefficients are located in addresses 0x00 to 0x7F and
are interpreted as 20-bit two’s complement numbers. When
writing the coefficient RAM, the lower addresses will be multi-
plied by relatively older data from the CIC5 and the higher
coefficient addresses will be multiplied by relatively newer data
from the CIC5. The coefficients need not be symmetric and the
coefficient length, N
taps
, may be even or odd. If the coefficients
are symmetric, then both sides of the impulse response must be
written into the coefficient RAM.
Although the base memory for coefficients is only 128 words long,
the actual length is 256 words long. There are two pages, each of
128 words long. The page is selected by Bit 8 of 0xA4. Although
this data must be written in pages, the internal core handles filters
that exceed the length of 128 taps. Therefore, the full length
of the data RAM may be used as the filter length (160 taps).
The RCF stores the data from the CIC5 into a 160
×
40 RAM.
160
×
20 is assigned to I data and 160
×
20 is assigned to Q data.
The RCF uses the RAM as a circular buffer, so it is difficult to know
in which address a particular data element is stored.
When the RCF is triggered to calculate a filter output, it starts by
multiplying the oldest value in the data RAM by the first coeffi-
cient, which is pointed to by the RCF Coefficient Offset Register
(0xA3). This value is accumulated with the products of newer
data-words multiplied by the subsequent locations in the coefficient
RAM until the coefficient address RCF
OFF
+ N
taps
–1 is reached.
Table V. Three-Tap Filter
Coefficient Address
Impulse Response
Data
0
1
2 = (N
taps
–1)
h(0)
h(1)
h(2)
N(0) oldest
N(1)
N(2) newest
The RCF Coefficient Offset register can be used for two purposes.
The main purpose of this register is to allow for multiple filters
to be loaded into memory and selected simply by changing the
offset as a pointer for rapid filter changes. The other use of this
register is to form part of the symbol timing adjustment. If the
desired filter length is padded with zeros on the ends, the starting
point can be adjusted to form slight delays in when the filter is
computed with reference to the high speed clock. This allows for
vernier adjustment of the symbol timing. Course adjustments can
be made with the RCF Decimation Phase.
The output rate of this filter is determined by the output rate of
the CIC5 stage and
M
RCF
.
f
f
M
SAMPR
SAMP
RCF
=
5
RCF Output Scale Factor and Control Register
Register 0xA4 is a compound register and is used to configure
several aspects of the RCF register. Bits 3–0 are used to set the
scale of the fixed-point output mode. This scale value may also
be used to set the floating-point outputs in conjunction with
Bit 6 of this register.
Bits 4 and 5 determine the output mode. Mode 00 sets up the chip
in fixed-point mode. The number of bits is determined by the
parallel or link port configuration.
Mode 01 selects floating-point mode 8 + 4. In this mode, an 8-bit
mantissa is followed by a 4-bit exponent. In mode 1x (x is don’t
care), the mode is 12 + 4, or 12-bit mantissa and 4-bit exponent.
Table VI. Output Mode Formats
Floating Point 12 + 4
Floating Point 8 + 4
Fixed Point
1x
01
00
Normally, the AD6634 will determine the exponent value that
optimizes numerical accuracy. However, if Bit 6 is set, the value
stored in Bits 3–0 is used to scale the output. This ensures
consistent scaling and accuracy during conditions that may warrant
predictable output ranges. If Bits 3–0 are represented by RCF
Scale, the scaling factor in dB is given by:
=
(
Scaling Factor
RCF Scale
dB
)
×
( )
2
– 3
20
log
10
相关PDF资料 |
PDF描述 |
|---|---|
| AD6634BBC | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6634PCB | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6635BB | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6636 | 150 MSPS Wideband Digital Down-Converter (DDC) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6634BBC | 功能描述:IC RSP 80MSPS DUAL 196-CSPBGA RoHS:否 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BBCZ | 功能描述:IC RSP 80MSPS DUAL 196CSPBGA RoHS:是 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BC/PCB | 制造商:Analog Devices 功能描述:WCDMA RECEIVE SGNL PROCESSOR - Bulk |
| AD6634PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
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