- 您现在的位置：买卖IC网 > PDF目录373890 > AD6634 (Analog Devices, Inc.) 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) PDF资料下载
参数资料
| 型号： | AD6634 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 基带处理器 |
| 英文描述： | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| 中文描述： | 80 MSPS的双通道的WCDMA接收信号处理器（RSP） |
| 文件页数： | 51/52页 |
| 文件大小： | 925K |
| 代理商： | AD6634 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页当前第51页第52页
REV. 0
AD6634
–51–
t
SSI
CLKn
X
FRAME
SCLK
SDI
FRAME
X
X
X
X
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Figure 47. Serial Word Structure and Serial Port Control Timing
JTAG BOUNDARY SCAN
The AD6634 supports a subset of IEEE Standard 1149.1 speci-
fication. For additional details of the standard, please see “IEEE
Standard Test Access Port and Boundary-Scan Architecture,”
IEEE-1149 publication from IEEE.
The AD6634 has five pins associated with the JTAG interface.
These pins are used to access the on-chip Test Access Port and
are listed in Table XVIII. All input JTAG pins are pull-up
except for TCLK, which is a pull-down.
Table XVIII. Boundary Scan Test Pins
Name
Pin Number
Description
TRST
TCLK
TMS
TDI
TDO
67
68
69
72
70
Test Access Port Reset
Test Clock
Test Access Port Mode Select
Test Data Input
Test Data Output
The AD6634 supports six op codes as shown in Table XIX.
These instructions set the mode of the JTAG interface.
Table XIX. Boundary Scan Op Codes
Instruction
Op Code
IDCODE
BYPASS
SAMPLE/PRELOAD
EXTEST
HIGHZ
CLAMP
001
111
010
000
011
100
The Vendor Identification Code can be accessed through the
IDCODE instruction and has the format shown in Table XX.
Table XX. Vendor ID Code
MSB
Version
Part
Number
Manufacturing
ID #
LSB
Mandatory
0000
0010
0111
1000
1100
000 1110 0101
1
A BSDL file for this device is available. Please contact Analog
Devices for more information.
EXTEST (3'b000)—Places the IC into an external boundary-test
mode and selects the boundary-scan register to be connected
between TDI and TDO. During this, the boundary-scan register
is accessed to drive test data off-chip via boundary outputs and
receive test data off-chip from boundary inputs.
IDCODE (3'b001)—Allows the IC to remain in its functional
mode and selects device ID register to be connected between TDI
and TDO. Accessing the ID register does not interfere with the
operation of the IC.
SAMPLE/PRELOAD (3'b010)—Allows the IC to remain in
normal functional mode and selects the boundary-scan register
to be connected between TDI and TDO. The boundary-scan
register can be accessed by a scan operation to take a sample of
the functional data entering and leaving the IC. Also, test data
can be preloaded into the boundary scan register before an
EXTEST instruction.
HIGHZ (3'b011)—Sets all outputs to high impedance state. Selects
1-bit bypass register to be connected between TDI and TDO.
CLAMP (3'b100)—Sets the outputs of the IC to logic levels
determined by the boundary-scan register and selects 1-bit bypass
register to be connected between TDI and TDO. Before this
instruction, boundary-scan data can be preloaded with the
SAMPLE/PRELOAD instruction.
BYPASS (3'b111)—Allows the IC to remain in normal functional
mode and selects 1-bit bypass register between TDI and TDO.
During this instruction, serial data is transferred from TDI to TDO
without affecting operation of the IC.
INTERNAL WRITE ACCESS
Up to 20 bits of data (as needed) can be written by the process
described below. Any high order bytes that are needed are written
to the corresponding data registers defined in the external 3-bit
address space. The least significant byte is then written to DR0
at address (000). When a write to DR0 is detected, the internal
microprocessor port state machine then moves the data in
DR2–DR0 to the internal address pointed to by the address in
the LAR and AMR.
Write Pseudocode
void write_micro(ext_address, int data);
main();
{
/
*
This code shows the programming of the NCO phase offset
register using the write_micro function as defined above. The
variable address is the External Address A[2:0] and data is the
value to be placed in the external interface register.
相关PDF资料 |
PDF描述 |
|---|---|
| AD6634BBC | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6634PCB | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6635BB | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6636 | 150 MSPS Wideband Digital Down-Converter (DDC) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6634BBC | 功能描述:IC RSP 80MSPS DUAL 196-CSPBGA RoHS:否 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BBCZ | 功能描述:IC RSP 80MSPS DUAL 196CSPBGA RoHS:是 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BC/PCB | 制造商:Analog Devices 功能描述:WCDMA RECEIVE SGNL PROCESSOR - Bulk |
| AD6634PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
发布紧急采购，3分钟左右您将得到回复。