- 您现在的位置：买卖IC网 > PDF目录373890 > AD6634 (Analog Devices, Inc.) 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) PDF资料下载
参数资料
| 型号： | AD6634 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 基带处理器 |
| 英文描述： | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| 中文描述： | 80 MSPS的双通道的WCDMA接收信号处理器（RSP） |
| 文件页数： | 47/52页 |
| 文件大小： | 925K |
| 代理商： | AD6634 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页当前第47页第48页第49页第50页第51页第52页
REV. 0
AD6634
–47–
channel, which is determined by the decimation rate of each
channel. The channel output indicator pins can be used to
determine which data came from which channel.
Bit 5 determines the format of the output data-words. When Bit 5 = 0,
parallel port A outputs 16-bit words on its 16-bit bus. This means
that I and Q data are interleaved and the IQ indicator pin determines
whether data on the port is I data or Q data. When Bit 5 = 1, parallel
port A is outputting an 8-bit I word and an 8-bit Q word at the
same time, and the IQ indicator pins will be HIGH.
0x1B Link Port Control A
Data is output through either a parallel port interface or a link
port interface. The link port provides an efficient data link
between the AD6634 and a TigerSHARC DSP and can be
enabled by setting Bit 7 = 1.
Bit 0 selects which data is output on link port A. When Bit 0 = 0,
link port A outputs data from the RCF according to the format
specified by Bit 1. When Bit 0 = 1, link port A outputs the data
from the AGCs according to the format specified by Bits 1 and 2.
Bit 1 has two different meanings that depend on whether data is
coming from the AGCs or from the RCFs. When data is coming
from the RCFs (Bit 0 = 0), Bit 1 selects between 2- and 4-channel
data mode. Bit 1 = 1 indicates link port A transmits RCF IQ words
alternately from channels 0 and 1. When Bit 1 = 1, link port A
outputs RCF IQ words from each of the four channels in succes-
sion: 0, 1, 2, then 3. However, when AGC data is selected (Bit
0 = 1), Bit 1 selects the AGC data output mode. In this mode,
when Bit 1 = 1, link port A outputs AGC A IQ and gain words.
With this mode, gain words must be included by setting Bit
2 = 0. However, if Bit 0 = Bit 1 = 0, then AGC A and B are
alternately output on link port A and the inclusion or exclusion of
the gain words is determined by Bit 2.
Bit 2 selects if RSSI words are included or not in the data output.
If Bit 1 = 1, Bit 2 = 0. Since the RSSI words are only two bytes
long and the IQ words are four bytes long, the RSSI words are
padded with zeros to give a full 16-byte TigerSHARC quad-word.
If AGC output is not selected (Bit 0 = 0), this bit can be any value.
Bits 6 through 3 specify the programmable delay value for link
port A between the time the link port receives a data ready from
the receiver and the time it transmits the first data-word. The
link port must wait at least six cycles of the receiver’s clock, so
this value allows the user to use clocks of differing frequency
and phase for the AD6634 link port and the TigerSHARC link
port. There is more information on the limitations and relationship
of these clocks in the section on Link Ports.
0x1C Parallel Port Control B
Data is output through either a parallel port interface or a link port
interface. When 0x1D Bit 7 = 0, the use of link port B is disabled
and the use of parallel port B is enabled. The parallel port pro-
vides different data modes for interfacing with DSPs or FPGAs.
Bit 0 selects which data is output on parallel port B. When
Bit 0 = 0, parallel port B outputs data from the RCF according
to the format specified by Bits 1 through 4. When Bit 0 = 1,
parallel port B outputs the data from the AGCs according to the
format specified by Bits 1 and 2.
In AGC mode, Bit 0 = 1 and Bit 1 determines if parallel port B
is able to output data from AGC A and Bit 2 determines if parallel
port B is able to output data from AGC B. The order of output
depends on the rate of triggers from each AGC, which in turn is
determined by the decimation rate of the channels feeding it. In
channel mode, Bit 0 = 0 and Bits 1 through 4 determine which
combination of the four processing channels is output. The
output order depends on the rate of triggers received from each
channel, which is determined by the decimation rate of each
channel. The channel output indicator pins can be used to
determine which data came from which channel.
Bit 5 determines the format of the output data words. When Bit
5 = 0, parallel port B outputs 16-bit words on its 16-bit bus. This
means that I and Q data are interleaved and the IQ indicator pin
determines whether data on the port is I data or Q data. When Bit
5 = 1, parallel port B is outputting an 8-bit I word and an 8-bit Q
word at the same time, and the IQ indicator pins will be HIGH.
0x1D Link Port Control B
Data is output through either a parallel port interface or a link port
interface. The link port provides an efficient data link between
the AD6634 and a TigerSHARC DSP and can be enabled by
setting Bit 7 = 1.
Bit 0 selects which data is output on link port B. When Bit 0 = 0,
link port B outputs data from the RCF according to the format
specified by bit 1. When Bit 0 = 1, link port B outputs the data
from the AGCs according to the format specified by Bits 1 and 2.
Bit 1 has two different meanings that depend on whether data is
coming from the AGCs or from the RCFs. When data is coming
from the RCFs (Bit 0 = 0), Bit 1 selects between 2- and 4- channel
data mode. Bit 1 = 1 indicates link port A transmits RCF IQ words
alternately from channels 0 and 1. When Bit 1 = 1, link port B out-
puts RCF IQ words from each of the four channels in succession:
0, 1, 2, then 3. However, when AGC data is selected (Bit 0 = 1),
Bit 1 selects the AGC data output mode. In this mode, when
Bit 1 = 1, link port B outputs AGC B IQ and gain words. With
this mode, gain words must be included by setting Bit 2 = 0.
However, if Bit 0 = Bit 1 = 0, then AGC A and B are alternately
output on link port B and the inclusion or exclusion of the gain
words is determined by Bit 2.
Bit 2 selects if RSSI words are included or not in the data output.
If Bit 1 = 1, Bit 2 = 0. Since the RSSI words are only two bytes long
and the IQ words are four bytes long, the RSSI words are padded
with zeros to give a full 16-byte TigerSHARC quad-word. If AGC
output is not selected (Bit 0 = 0) then this bit can be any value.
Bits 6 through 3 specify the programmable delay value for link
port B between the time the link port receives a data ready from
the receiver and the time it transmits the first data-word. The link
port must wait at least six cycles of the receiver’s clock, so this
value allows the user to use clocks of differing frequency and phase
for the AD6634 link port and the TigerSHARC link port. There
is more information on the limitations and relationship of these
clocks in the section on Link Ports.
0x1E Port Clock Control
Bit 0 determines whether PCLK is supplied externally by the user
or derived internally in the AD6634. If PCLK is derived internally
from CLK (Bit 0 = 1), it is output through the PCLK pin as a
master clock. For most applications, PCLK will be provided by
the user as an input to the AD6634 via the PCLK pin.
Bits 2 and 1 allow the user to divide CLK by an integer value to
generate PCLK (00 = 1, 01 = 2, 10 = 4, 11 = 8).
相关PDF资料 |
PDF描述 |
|---|---|
| AD6634BBC | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6634PCB | 80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6635BB | 4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
| AD6636 | 150 MSPS Wideband Digital Down-Converter (DDC) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD6634BBC | 功能描述:IC RSP 80MSPS DUAL 196-CSPBGA RoHS:否 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BBCZ | 功能描述:IC RSP 80MSPS DUAL 196CSPBGA RoHS:是 类别:RF/IF 和 RFID >> RF 混频器 系列:AD6634 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:100 系列:- RF 型:W-CDMA 频率:2.11GHz ~ 2.17GHz 混频器数目:1 增益:17dB 噪音数据:2.2dB 次要属性:- 电流 - 电源:11.7mA 电源电压:2.7 V ~ 3.3 V 包装:托盘 封装/外壳:12-VFQFN 裸露焊盘 供应商设备封装:12-QFN-EP（3x3） |
| AD6634BC/PCB | 制造商:Analog Devices 功能描述:WCDMA RECEIVE SGNL PROCESSOR - Bulk |
| AD6634PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) |
| AD6635 | 制造商:AD 制造商全称:Analog Devices 功能描述:4-Channel, 80 MSPS WCDMA Receive Signal Processor (RSP) |
发布紧急采购，3分钟左右您将得到回复。