- 您现在的位置：买卖IC网 > PDF目录9158 > AD9517-3ABCPZ (Analog Devices Inc)IC CLOCK GEN 2.0GHZ VCO 48LFCSP PDF资料下载
参数资料
| 型号： | AD9517-3ABCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.0GHZ VCO 48LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:12 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
Data Sheet
AD9517-3
Rev. E | Page 35 of 80
In differential mode, the reference input pins are internally self-
biased so that they can be ac-coupled via capacitors. It is possible to
dc couple to these inputs. If the differential REFIN is driven by
a single-ended signal, the unused side (REFIN) should be
decoupled via a suitable capacitor to a quiet ground. Figure 49
shows the equivalent circuit of REFIN.
VS
REF1
REF2
REFIN
150
10k
12k
10k
REFIN
85k
VS
85k
VS
06
42
7-
0
66
Figure 49. REFIN Equivalent Circuit
Reference Switchover
The AD9517 supports dual single-ended CMOS inputs, as well
as a single differential reference input. In the dual single-ended
reference mode, the AD9517 supports automatic and manual
PLL reference clock switching between REF1 (on Pin REFIN)
and REF2 (on Pin REFIN). This feature supports networking
and other applications that require smooth switching of redundant
references. When used in conjunction with the automatic
holdover function, the AD9517 can achieve a worst-case
reference input switchover with an output frequency disturbance as
low as 10 ppm.
When using reference switchover, the single-ended reference
inputs should be dc-coupled CMOS levels and never be allowed
to go to high impedance. If these inputs are allowed to go to high
impedance, noise may cause the buffer to chatter, causing a false
detection of the presence of a reference.
Reference switchover can be performed manually or auto-
matically. Manual switchover is performed either through
Register 0x01C or by using the REF_SEL pin. Manual switchover
requires the presence of a clock on the reference input that is
being switched to, or that the deglitching feature be disabled
(Register 0x01C[7]). The reference switching logic fails if this
condition is not met, and the PLL does not reacquire.
Automatic revertive switchover relies on the REFMON pin to
indicate when REF1 disappears. By programming Register 0x01B =
0xF7 and Register 0x01C = 0x26, the REFMON pin is programmed
to be high when REF1 is invalid, which commands the switch to
REF2. When REF1 is valid again, the REFMON pin goes low, and
the part again locks to REF1. It is also possible to use the STATUS
pin for this function, and REF2 can be used as the preferred
reference.
A switchover deglitch feature ensures that the PLL does not
receive rising edges that are far out of alignment with the newly
selected reference.
Automatic nonrevertive switching is not supported.
Reference Divider R
The reference inputs are routed to the reference divider, R.
R (a 14-bit counter) can be set to any value from 0 to 16383
by writing to Register 0x011 and Register 0x012. (Both R = 0 and
R = 1 give divide-by-1.) The output of the R divider goes to one
of the PFD inputs to be compared to the VCO frequency
divided by the N divider. The frequency applied to the PFD
must not exceed the maximum allowable frequency, which
depends on the antibacklash pulse setting (see Table 2).
The R counter has its own reset. R counter can be reset using
the shared reset bit of the R, A, and B counters. It can also be
reset by a SYNC operation.
VCXO/VCO Feedback Divider N—P, A, B, R
The N divider is a combination of a prescaler (P) and two
counters, A and B. The total divider value is
N = (P × B) + A
where the value of P can be 2, 4, 8, 16, or 32.
Prescaler
The prescaler of the AD9517 allows for two modes of operation:
a fixed divide (FD) mode of 1, 2, or 3, and dual modulus (DM)
mode where the prescaler divides by P and (P + 1) {2 and 3,
4 and 5, 8 and 9, 16 and 17, or 32 and 33}. The prescaler modes
of operation are given in Table 54, Register 0x016[2:0]. Not all
modes are available at all frequencies (see Table 2).
When operating the AD9517 in dual modulus mode (P//P + 1),
the equation used to relate input reference frequency to VCO
output frequency is
fVCO = (fREF/R) × (P × B + A) = fREF × N/R
However, when operating the prescaler in an FD mode of 1,
2, or 3, the A counter is not used (A = 0) and the equation
simplifies to
fVCO = (fREF/R) × (P × B) = fREF × N/R
When A = 0, the divide is a fixed divide of P = 2, 4, 8, 16, or 32,
in which case the previous equation also applies.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9517-1ABCPZ | IC CLOCK GEN 2.5GHZ VCO 48LFCSP |
| V110A48H300BL2 | CONVERTER MOD DC/DC 48V 300W |
| AD9511BCPZ | IC CLOCK DIST 5OUT PLL 48LFCSP |
| V110A48H300BL | CONVERTER MOD DC/DC 48V 300W |
| VI-B60-MV | CONVERTER MOD DC/DC 5V 150W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9517-3ABCPZ | 制造商:Analog Devices 功能描述:CLOCK GENERATOR 2.25GHZ LFCSP-48 制造商:Analog Devices 功能描述:CLOCK GENERATOR, 2.25GHZ, LFCSP-48 |
| AD9517-3ABCPZ-RL7 | 功能描述:IC CLOCK GEN 2.0GHZ VCO 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9517-3BCPZ | 制造商:Analog Devices 功能描述: |
| AD9517-3BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9517-3BCPZ-TR | 制造商:Analog Devices 功能描述:12-OUTPUT CLOCK GENERATOR WITH INTEGRATED 2.0 GHZ VCO - Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。