- 您现在的位置：买卖IC网 > PDF目录9158 > AD9517-3ABCPZ (Analog Devices Inc)IC CLOCK GEN 2.0GHZ VCO 48LFCSP PDF资料下载
参数资料
| 型号： | AD9517-3ABCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 62/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.0GHZ VCO 48LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:12 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页当前第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页
Data Sheet
AD9517-3
Rev. E | Page 65 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
2
REF2 power-on
This bit turns the REF2 power on.
0: REF2 power off (default).
1: REF2 power on.
1
REF1 power-on
This bit turns the REF1 power on.
0: REF1 power off (default).
1: REF1 power on.
0
Differential
reference
Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic
switchover between REF1 and REF2 to work.
0: single-ended reference mode (default).
1: differential reference mode.
0x01D
4
PLL status
Disables the PLL status register readback.
register disable
0: PLL status register enable (default).
1: PLL status register disable.
3
LD pin comparator
enable
Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When
in the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if
the PLL was previously in a locked state (see Figure 53). Otherwise, this function can be used with the REFMON and
STATUS pins to monitor the voltage on this pin.
0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true (high) (default).
1: enables LD pin comparator.
2
Holdover enable
Along with Bit 0, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
1
External
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
holdover control
0: automatic holdover mode—holdover controlled by automatic holdover circuit. (default)
1: external holdover mode—holdover controlled by SYNC pin.
0
Holdover enable
Along with Bit 2, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
0x01F
6
VCO cal finished
Read-only register: indicates status of the VCO calibration.
0: VCO calibration not finished.
1: VCO calibration finished.
5
Holdover active
Read-only register: indicates if the part is in the holdover state (see Figure 53). This is not the same as holdover enabled.
0: not in holdover.
1: holdover state active.
4
REF2 selected
Read-only register: indicates which PLL reference is selected as the input to the PLL.
0: REF1 selected (or differential reference if in differential mode).
1: REF2 selected.
3
VCO frequency >
threshold
Read-only register: indicates if the VCO frequency is greater than the threshold (see Table 16: REF1, REF2, and VCO
frequency status monitor).
0: VCO frequency is less than the threshold.
1: VCO frequency is greater than the threshold.
2
REF2 frequency >
threshold
Read-only register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by
Register 0x1A, Bit 6.
0: REF2 frequency is less than threshold frequency.
1: REF2 frequency is greater than threshold frequency.
1
REF1 frequency >
threshold
Read-only register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A, Bit 6.
0: REF1 frequency is less than threshold frequency.
1: REF1 frequency is greater than threshold frequency.
0
Digital lock detect
Read-only register: digital lock detect.
0: PLL is not locked.
1: PLL is locked.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9517-1ABCPZ | IC CLOCK GEN 2.5GHZ VCO 48LFCSP |
| V110A48H300BL2 | CONVERTER MOD DC/DC 48V 300W |
| AD9511BCPZ | IC CLOCK DIST 5OUT PLL 48LFCSP |
| V110A48H300BL | CONVERTER MOD DC/DC 48V 300W |
| VI-B60-MV | CONVERTER MOD DC/DC 5V 150W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9517-3ABCPZ | 制造商:Analog Devices 功能描述:CLOCK GENERATOR 2.25GHZ LFCSP-48 制造商:Analog Devices 功能描述:CLOCK GENERATOR, 2.25GHZ, LFCSP-48 |
| AD9517-3ABCPZ-RL7 | 功能描述:IC CLOCK GEN 2.0GHZ VCO 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9517-3BCPZ | 制造商:Analog Devices 功能描述: |
| AD9517-3BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9517-3BCPZ-TR | 制造商:Analog Devices 功能描述:12-OUTPUT CLOCK GENERATOR WITH INTEGRATED 2.0 GHZ VCO - Tape and Reel |
发布紧急采购，3分钟左右您将得到回复。