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| 型号： | AD9517-3ABCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 58/80页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK GEN 2.0GHZ VCO 48LFCSP |
| 标准包装： | 1 |
| 类型： | 时钟发生器，扇出配送 |
| PLL： | 是 |
| 输入： | CMOS，LVDS，LVPECL |
| 输出： | CMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:12 |
| 差分 - 输入:输出： | 是/是 |
| 频率 - 最大： | 2.25GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
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Data Sheet
AD9517-3
Rev. E | Page 61 of 80
Reg.
Addr.
(Hex)
Bits
Name
Description
0x016
[2:0]
Prescaler P
Prescaler: DM = dual modulus and FD = fixed divide.
2
1
0
Mode
Prescaler
0
FD
Divide-by-1.
0
1
FD
Divide-by-2.
0
1
0
DM
Divide-by-2 (2/3 mode).
0
1
DM
Divide-by-4 (4/5 mode).
1
0
DM
Divide-by-8 (8/9 mode).
1
0
1
DM
Divide-by-16 (16/17 mode).
1
0
DM
Divide-by-32 (32/33 mode) (default).
1
FD
Divide-by-3.
0x017
[7:2]
STATUS pin
Selects the signal that is connected to the STATUS pin.
control
7
6
5
4
3
2
Level or
Dynamic
Signal
Signal at STATUS Pin
0
LVL
Ground (dc) (default).
0
1
DYN
N divider output (after the delay).
0
1
0
DYN
R divider output (after the delay).
0
1
DYN
A divider output.
0
1
0
DYN
Prescaler output.
0
1
0
1
DYN
PFD up pulse.
0
1
0
DYN
PFD down pulse.
0
X
LVL
Ground (dc); for all other cases of 0XXXXXb not specified above.
The selections that follow are the same as REFMON.
1
0
LVL
Ground (dc).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active
high.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode);
active high.
1
0
1
LVL
Status REF1 frequency (active high).
1
0
1
0
LVL
Status REF2 frequency (active high).
1
0
1
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
LVL
Status of VCO frequency (active high).
1
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
0
1
LVL
Digital lock detect (DLD); active high.
1
0
1
0
LVL
Holdover active (active high).
1
0
1
LVL
LD pin comparator output (active high).
1
0
LVL
VS (PLL supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active low.
1
0
1
LVL
Status of REF1 frequency (active low).
1
0
LVL
Status of REF2 frequency (active low).
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
LVL
Status of VCO frequency (active low).
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
Digital lock detect (DLD) (active low).
1
0
LVL
Holdover active (active low).
1
LVL
LD pin comparator output (active low).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9517-3ABCPZ | 制造商:Analog Devices 功能描述:CLOCK GENERATOR 2.25GHZ LFCSP-48 制造商:Analog Devices 功能描述:CLOCK GENERATOR, 2.25GHZ, LFCSP-48 |
| AD9517-3ABCPZ-RL7 | 功能描述:IC CLOCK GEN 2.0GHZ VCO 48LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 时钟发生器 PLL:带旁路 输入:LVCMOS，LVPECL 输出:LVCMOS 电路数:1 比率 - 输入:输出:2:11 差分 - 输入:输出:是/无 频率 - 最大:240MHz 除法器/乘法器:是/无 电源电压:3.135 V ~ 3.465 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:32-LQFP 供应商设备封装:32-TQFP（7x7） 包装:带卷 (TR) |
| AD9517-3BCPZ | 制造商:Analog Devices 功能描述: |
| AD9517-3BCPZ-REEL7 | 制造商:Analog Devices 功能描述: |
| AD9517-3BCPZ-TR | 制造商:Analog Devices 功能描述:12-OUTPUT CLOCK GENERATOR WITH INTEGRATED 2.0 GHZ VCO - Tape and Reel |
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