参数资料
型号: AD9600ABCPZ-105
厂商: Analog Devices Inc
文件页数: 5/72页
文件大小: 0K
描述: IC ADC 10BIT 105MSPS 64LFCSP
标准包装: 1
位数: 10
采样率(每秒): 105M
数据接口: 串行,SPI?
转换器数目: 2
功率耗散(最大): 650mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 托盘
输入数目和类型: 4 个单端,单极;2 个差分,单极
AD9600
Rev. B | Page 13 of 72
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
0
69
09-
00
2
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D1A
D2A
D3A
DRG
ND
DRV
DD
D4A
D5A
DV
DD
D6A
D7A
D8A
(M
SB
)D
9
A
FD
0
A
FD
1
A
FD
2
A
FD
3
A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DR
G
ND
D1
B
D0
B
(
L
S
B
)
DN
C
DN
C
DN
C
DN
C
DV
D
FD
3
B
FD
2
B
FD
1
B
FD
0
B
SY
N
C
CS
B
CL
K
CL
K
+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DRVDD
D2B
D3B
D4B
D5B
D6B
D7B
D8B
(MSB) D9B
DCOB
DCOA
DNC
(LSB) D0A
SCLK/DFS
SDIO/DCS
AVDD
VIN + B
VIN – B
RBIAS
CML
SENSE
VREF
VIN – A
VIN + A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PIN 1
INDICATOR
AD9600
PARALLEL CMOS
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
Figure 6. Parallel CMOS Mode Pin Configuration (Top View)
Table 8. Parallel CMOS Mode Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
20, 64
DRGND
Ground
Digital Output Ground.
1, 21
DRVDD
Supply
Digital Output Driver Supply (1.8 V to 3.3 V).
24, 57
DVDD
Supply
Digital Power Supply (1.8 V Nominal).
36, 45, 46
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
0
AGND
Ground
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
ADC Inputs
37
VIN + A
Input
Differential Analog Input Pin (+) for Channel A.
38
VIN A
Input
Differential Analog Input Pin () for Channel A.
44
VIN + B
Input
Differential Analog Input Pin (+) for Channel B.
43
VIN B
Input
Differential Analog Input Pin () for Channel B.
39
VREF
I/O
Voltage Reference Input/Output.
40
SENSE
Input
Voltage Reference Mode Select (see Table 11 for details).
42
RBIAS
Input
External Reference Bias Resistor.
41
CML
Output
Common-Mode Level Bias Output for Analog Inputs.
49
CLK+
Input
ADC Master Clock True. The ADC clock can be driven using a single-ended
CMOS (see Figure 60 and Figure 61 for the recommended connection).
50
CLK
Input
ADC Master Clock Complement. The ADC clock can be driven using a single-
ended CMOS (see Figure 60 and Figure 61 for the recommended connection).
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