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| 型号： | AD9895KBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/58页 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFBGA，CSPBGA |
| 供应商设备封装： | 64-CSPBGA（9x9） |
| 包装： | 带卷 (TR) |
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REV. A
–26–
AD9891/AD9895
Table XIII contains the summary of the VSG Registers. The
AD9891/AD9895 has eight SG outputs, VSG1–VSG8. Each of
the outputs can be assigned to one of four programmed
sequences by using the SGSEL1–SGSEL8 Registers. Each
sequence is generated in the same manner as the individual vertical
sequences, with a programmable start polarity (SGPOL), first toggle
position (SGTOG1), and second toggle position (SGTOG2).
The active line where the VSG1–VSG8 pulses occur is program-
mable using the two SGACTLIN Registers. Additionally, any
of the VSG1–VSG8 pulses may be individually disabled by
using the SGMASK Register. The masking allows all of the differ-
ent SG sequences to be preprogrammed and the appropriate
pulses for odd or even fields can be masked.
SHUTTER TIMING CONTROL
CCD image exposure time is controlled through use of the substrate
clock signal (SUBCK), which pulses the CCD substrate to clear
out accumulated charge. The AD9891/AD9895 supports three
types of electronic shuttering: Normal Shutter Mode, High Preci-
sion Shutter Mode, and Low Speed Shutter Mode. Along with the
SUBCK pulse placement, the AD9891/AD9895 can accommo-
date different progressive and interlaced readout modes.
Additionally, the AD9891/AD9895 provides output signals to
control an external mechanical shutter, strobe (flash), and the
CCD bias for still mode readout (VSUB).
Normal Shutter Mode
Figure 30 shows the VD and SUBCK output for Normal Shut-
ter Mode. The SUBCK will pulse once per line, and the total
number of repetitions within the field is programmable. The
pulse polarity, width, and line location is programmable using
the SUBCKPOL, SUBCK1TOG1, and SUBCK1TOG2 Regis-
ters (see Table XIV). The number of SUBCK pulses per field is
programmed in the SUBCKNUM Register.
As shown in Figure 30, the SUBCK pulses will always begin
on the line after the sensor gates occur, specified by the
SGACTLINE Register (Addr x265 and Addr x266). The
SUBCKPOL, SUBCK1TOG, SUBCK2TOG, and
SUBCKNUM Registers are updated at the start of the line after
the sensor gate line. All other shutter mode registers are up-
dated with the majority of the AD9891/AD9895’s registers at
the VD/HD falling edge.
High Precision Shutter Mode
High precision shuttering is controlled in the same way as nor-
mal shuttering but requires a second set of toggle registers. In
this mode, the SUBCK still pulses once per line, but the last
SUBCK in the field will have an additional SUBCK pulse
whose location is determined by the SUBCK2TOG1 and
SUBCK2TOG2 Registers (see Figure 31). Finer resolution of
the exposure time is possible using this mode. Leaving both
SUBCK2TOG Registers set to 4095 (x3F) will disable the High
Precision Mode (default setting).
Low Speed Shutter Mode
For normal exposure times less than one field interval, the
EXPOSURE Register will be set to 0. Exposure times greater
than one field interval can be achieved by writing a value
greater than zero to the EXPOSURE Register. As shown in
Figure 32, this shutter mode will suppress the SUBCK and
VSG outputs for up to 4095 fields (VD periods). The VD and
HD outputs may be suppressed during the exposure period by
programming the VDHDOFF Register to 1.
VD
SUBCK
SUBCK PROGRAMMABLE SETTINGS:
1: PULSE POLARITY USING THE SUBCKPOL REGISTER
2: NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER
3: PIXEL LOCATION OF PULSE WITHIN THE LINE AND PULSE WIDTH PROGRAMMED USING SUBCK1 TOGGLE POSITION REGISTERS
t
EXP
VSG1–
VSG8
HD
t
EXP
Figure 30. Normal Shutter Mode
VD
SUBCK
NOTES
1. 2ND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE.
2. LOCATION OF 2ND PULSE IS FULLY PROGRAMMABLE USING THE SUBCK2 TOGGLE POSITION REGISTERS.
VSG1–
VSG8
HD
t
EXP
t
EXP
Figure 31. High Precision Shutter Mode
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