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参数资料
| 型号： | AD9895KBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 38/58页 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFBGA，CSPBGA |
| 供应商设备封装： | 64-CSPBGA（9x9） |
| 包装： | 带卷 (TR) |
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REV. A
AD9891/AD9895
–43–
Table XIX. AFE Register Map
Bit
Default
Address
Content
Width
Value
Register Name
Register Description
00
[5:0]
6
10
OPRMODE[5:0]
AFE Operation Mode (See Table XXXI.)
01
[1:0]
2
00
OPRMODE[7:6]
02
[5:0]
6
05
CCDGAIN[5:0]
VGA Gain (Defaults to 2 dB)
03
[3:0]
4
01
CCDGAIN[9:6]
04
[5:0]
6
00
REFBLACK[5:0]
Black Clamp Level
05
[1:0]
2
02
REFBLACK[7:6]
06
[5:0]
600
CTLMODE
Control Mode (See Table XXXI.)
07
[5:0]
6
00
PXGA GAIN0
PxGA Color 0 Gain
08
[5:0]
6
00
PXGA GAIN1
PxGA Color 1 Gain
09
[5:0]
6
00
PXGA GAIN2
PxGA Color 2 Gain
0A
[5:0]
6
00
PXGA GAIN3
PxGA Color 3 Gain
Table XX. MISCELLANEOUS/EXTRA Register Map
Bit
Default
Address
Content
Width
Value
Register Name
Register Description
010
[5:0]
6
00
INTIAL2
See Power-Up Sequence. Should be set to “4.”
017
[0]
1
00
SW_RESET
Software Reset (1 = Reset All Registers to Default)
018
[0]
1
00
OUT_CONT
Output Control (0 = Make All Outputs DC Inactive)
019
[5:0]
6
00
UPDATE[5:0]
Serial Data Update Control. Sets the line (HD)
within the field for the serial data update to occur.
01A
[5:0]
6
00
UPDATE[11:6]
01B
[0]
1
00
PREVENTUPDATE
Prevents the Update of the VD Updated Registers
01C
[0]
1
00
READBACK
Serial Interface Readback Enable
01D
[5:0]
6
00
DOUTPHASE
DOUT Phase Control
01E
[0]
1
00
DCLKMODE
DCLK Mode (0 = DCLK Tracks DOUT Phase,
1 = DCLK Is CLO, i.e., CLI Inverse)
01F
[0]
1
00
CLIDIVIDE
Divide CLI Input Clock by 2
020
[0]
1
00
DISABLERESTORE
Disable CCDIN DC Restore Circuit during PBLK
(1 = Disable)
021
[0]
1
01
FIELDVAL
Reset Internal Field Pulse Value (0 = Next Field
Odd, 1 = Next Field Even)
022
[0]
1
00
H1HBLKRETIME
Re-time H1/H2 HBLK to Internal H1 Clock
023
[0]
1
00
H3HBLKRETIME
Re-time H3/H4 HBLK to Internal H3 Clock
024
[0]
1
00
SYNCENABLE
External Synchronization Enable (1 = Enable)
025
[0]
1
00
SYNCPOL
SYNC Active Polarity (0 = Active LOW)
026
[0]
1
00
SYNCSUSPEND
Suspend Clocks during SYNC Active (1 = Suspend)
027
[0]
1
00
OUTPUTLD
Assign LD/FD Output (0 = FD, 1 = LD)
028
[0]
1
00
OUTPUTPBLK
Assign CLPOB/PBLK Output (0 = CLPOB,
1 = PBLK)
029
[0]
1
00
TGCORE_RSTB
TG Core Reset_bar (0 = Hold TG Core in Reset,
1 = Resume Operation)
02A
[0]
1
00
FTRANCCD
Frame Transfer CCD Mode (1 = VSG1–VSG4
Become V5–V8 Out)
02B
[5:0]
6
00
INTIAL1
See Power-Up Sequence. Should be set to “53.”
031
[0]
1
01
SINGLE_CLAMP
CLPDM = CLPOB when Set to 1 (Only CLPOB
Registers Used).
032
[1:0]
2
02
DOUT_DELAY
Delay from DCLK to DOUT (0 = No Delay,
1= 4 ns, 2 = 8 ns, 3 = 12 ns)
033
[0]
1
01
OSC_PWRDOWN
CLO Oscillator Power-Down (0 = Oscillator Is
Powered Down)
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