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| 型号： | AD9895KBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/58页 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFBGA，CSPBGA |
| 供应商设备封装： | 64-CSPBGA（9x9） |
| 包装： | 带卷 (TR) |
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REV. A
–16–
AD9891/AD9895
Table III. CLPOB, CLPDM, and PBLK Individual Sequence Parameters
Register
Length
Range
Description
SPOL
1b
High/Low
Starting Polarity of Vertical Transfer Pulse for Sequences 0–3
TOG1
12b
0–4095 Pixel Location
First Toggle Position within Line for Sequences 0–3
TOG2
12b
0–4095 Pixel Location
Second Toggle Position within Line for Sequences 0–3
Table IV. HBLK Individual Sequence Parameters
Register
Length
Range
Description
HBLKMASK
1b
High/Low
Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High)
HBLKTOG1
12b
0–4095 Pixel Location
First Toggle Position within Line for Sequences 0–3
HBLKTOG2
12b
0–4095 Pixel Location
Second Toggle Position within Line for Sequences 0–3
Table V. Horizontal Sequence Control Parameters for CLPOB, CLPDM, and PBLK
Register
Length
Range
Description
SCP1–SCP3
12b
0–4095 Line Number
CLPOB/PBLK SCP to Define Horizontal Regions 0–3
SPTR0–SPTR3
2b
0–3 Sequence Number
Sequence Pointer for Horizontal Regions 0–3
Table VI. Horizontal Sequence Control Parameters for HBLK
Register
Length
Range
Description
VTPRCP1–
12b
0–4095 Line Number
Vertical Region Change Positions (See Table IX.)
VTPRCP7
HBLKSPTR0–
2b
0–3 Sequence Number
Sequence Pointer for HBLK Regions 0–7
HBLKSPTR7
UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE PROGRAMMED WITH-
IN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS.
SEQUENCE CHANGE POSITION #1
SEQUENCE CHANGE POSITION #2
SEQUENCE CHANGE POSITION #3
SINGLE FIELD (1 VD INTERVAL)
CLAMP AND PBLK SEQUENCE REGION 1
SEQUENCE CHANGE POSITION #0
(V-COUNTER = 0)
CLAMP AND PBLK SEQUENCE REGION 4
CLAMP AND PBLK SEQUENCE REGION 3
CLAMP AND PBLK SEQUENCE REGION 2
Figure 16. Clamp and Blanking Sequence Flexibility
zontal sequences. Up to four SCPs are available to divide the
readout into four separate regions, as shown in Figure 16. The
SCP0 is always hard-coded to line 0, and SCP1–SCP3 are
register programmable. During each region bound by the SCP,
the SPTR Registers designate which sequence is used by each
signal. CLPOB and CLPDM share the same SCP, PBLK has a
separate set of SCP, and HBLK shares the vertical RCP (see
Vertical Timing Generation section). For example,
CLPSCP1 will define Region 0 for CLPOB and CLPDM,
and in that region any of the four individual CLPOB and
CLPDM sequences may be selected with the SPTR Registers.
The next SCP defines a new region, and in that region each
signal can be assigned to a different individual sequence. Be-
cause HBLK shares the vertical RCP, there are up to eight
regions where HBLK sequences may be changed using the eight
HBLKSPTR Registers.
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