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| 型号： | AD9895KBCZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 37/58页 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROC/GEN 64-CSPBGA |
| 标准包装： | 2,000 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFBGA，CSPBGA |
| 供应商设备封装： | 64-CSPBGA（9x9） |
| 包装： | 带卷 (TR) |
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REV. A
–42–
AD9891/AD9895
Table XVIII. SG-Line Updated Registers
Register
Description
SUBCKPOL
SUBCK Start Polarity
SUBCK1TOG1
SUBCK First Toggle Position
SUBCK1TOG2
SUBCK Second Toggle Position
SUBCK2TOG1
Second SUBCK First Toggle Position
SUBCK2TOG2
Second SUBCK Second Toggle Position
SUBCKNUM
Total Number of SUBCKs per Field
SUBCKSUPPRESS
Number of SUBCKs to Suppress after
VSG Line
NOTES ON REGISTER LISTING
1. Registers larger than six bits occupy two adjacent addresses.
When writing to these registers, the lower address contain-
ing the least significant data bits should be written to first.
The data for both addresses should be written to avoid
corruption of register data.
2. All addresses and default values are expressed in hexadecimal.
3. All registers are VD/HD updated as shown in Figure 52, except
for the registers indicated in Table XVII, which are SL updated.
4. The registers indicated in Table XVIII are not updated by
SL or VD/HD, but are updated at the HD line following
the VSG line.
Table XVII. SL-Updated Register
Register
Description
OPRMODE
AFE Operation Modes
CTLMODE
AFE Control Modes
SW_RESET
Software Reset Bit
READBACK
Enables Serial Register Readback
Mode
FIELDVAL
Resets Internal Field Pulse.
H1HBLKRETIME
Retimes the H1 HBLK to Internal
Clock
H3HBLKRETIME
Retimes the H3 HBLK to Internal
Clock
SYNCENABLE
External Synchronization Enable
SYNCPOL
External SYNC Active Polarity
SYNCSUSPEND
SYNC Suspend while Active
TG_CORE RSTB
Reset Bar Signal for Internal TG
Core
FFTRANCCD
Frame Transfer CCD Mode
H12POL
H1/H2 Polarity Control
H1POSLOC
H1 Positive Edge Location
H1NEGLOC
H1 Negative Edge Location
H34POL
H3/H4 Polarity Control
H3POSLOC
H3 Positive Edge Location
H3NEGLOC
H3 Negative Edge Location
H1DRV
H1 Drive Current
H2DRV
H2 Drive Current
H3DRV
H3 Drive Current
H4DRV
H4 Drive Current
RGPOL
RG Polarity
RGPOSLOC
RG Positive Edge Location
RGNEGLOC
RG Negative Edge Location
SHPLOC
SHP Sample Location
SHDLOC
SHD Sample Location
MASTER
VD/HD Master/Slave Timing Mode
VDHDPOL
VD/HD Active Polarity
SINGLE_CLAMP
Sets CLPDM = CLPOB
DOUT_DELAY
Sets the Output Delay of DOUT
OSC_PWRDOWN
Powers Down the CLO Oscillator
VDHDPOL
VD/HD Active Polarity
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