参数资料
| 型号： | ADM1060ARU |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/52页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVIS/SEQUENC 7-CH 28TSSOP |
| 标准包装： | 50 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 7 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 管件 |
| 配用： | EVAL-ADM1060EBZ-ND - BOARD EVALUATION ADM1060 |
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ADM1060
where
VPn
Voltage Range
V B (V)
V R (V)
0.6 V to 1.8 V
0.604
1.204
RANGE SELECT
DAC (1 OR 2 BITS)
OV
COMPARATOR
1 V to 3 V
2 V to 6 V
4.8 V to 14.4 V
1.003
2.005
4.849
1.999
3.997
9.666
VREF
GLITCH
FILTER
FAULT
OUTPUT
–2 V to –6 V –1.994 –3.995
V T is the desired threshold voltage (UV or OV)
DUAL 8-BIT
DAC FOR
SETTING UV
AND OV
THRESHOLDS
UV
COMPARATOR
FAULT TYPE
SELECT
V R is the threshold voltage range
N is the decimal value of the 8 bit code
V B is the bottom of threshold range
The code for a given threshold is therefore given by
N = 255 × ( V T – V B )/V R
For example, if the user wishes to set a 5 V OV threshold on
VP1, the code to be programmed in the PS1OVTH register
(discussed later) would be
N = 255 × (5 – 2.005)/3.997
Thus, N = 191 (1011 1111 binary, or 0xBF)
The available threshold ranges and their resolutions are shown
in Table 3. Note that the low end of the detection range is fixed
at 33.33% of the top of the range. Note also that for a given SFD,
the ranges overlap; for example, VH goes from 2 V to 6 V and
then from 4.8 V to 14.4 V. This is to provide better threshold
Figure 18. Positive Programmable Supply Fault Detector
SFD COMPARATOR HYSTERESIS
The OV and UV comparators shown in Figure 18 are always
looking at VPn via a potential divider. In order to avoid
chattering (multiple transitions when the input is very close to
the set threshold level), these comparators have digitally
programmable hysteresis. The UV and OV hysteresis can be
programmed in two registers that are similar but separate to the
UV or OV threshold registers. Only the five LSBs of these
registers can be set. The hysteresis is added after the supply
voltage goes out of tolerance. Thus, the user can determine how
much above the UV threshold the input must rise again before a
UV fault is deasserted. Similarly, the user can determine how
much below the OV threshold the input must fall again before
an OV fault is deasserted. The hysteresis figure is given by
V H = V R × N THRESH /255
setting resolution as supplies decrease in value.
where
Table 3. Input Threshold Ranges and Resolution
Input Name
VH
VBn
VPn
Voltage Ranges
4.8 V to 14.4 V
2 V to 6 V
2 V to 6 V
1 V to 3 V
?6 V to ?2 V
2 V to 6 V
1 V to 3 V
0.6 V to 1.8 V
Resolution
37.6 mV
15.6 mV
15.6 mV (Pos. Mode)
7.8 mV (Pos. Mode)
15.6 mV (Neg. Mode)
15.6 mV
7.8 mV
4.7 mV
V H is the desired hysteresis voltage
N THRESH is the decimal value of the 5-bit hysteresis code
Therefore, if the low range threshold detector was selected, the
max hysteresis is defined as
(3 V – 1 V) × 31/255 = 242 mV, where (2 5 – 1 = 31)
The hysteresis programming resolution is the same as the
threshold detect ranges—that is, 37.5 mV on the high range,
the case of a positive supply).
15.6 mV on the midrange, 7.8 mV on the low range, and 4.7 mV
on the ultralow range.
BIPOLAR SFDs
The two bipolar SFDs also allow the detection of faults on nega-
tive supplies. A polarity bit in the setup register for this SFD
(Bit 7 in Register BSnSEL—see register map overleaf) deter-
mines if a positive or negative input should be applied to VBn.
Only one range (?6 V to ?2 V) is available when the SFDs are in
negative mode. Note that the bipolar SFDs cannot be used to
power the ADM1060, even if the voltage on VBn is positive.
Rev. B | Page 12 of 52
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