参数资料
| 型号： | ADM1060ARU |
| 厂商： | Analog Devices Inc |
| 文件页数： | 40/52页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVIS/SEQUENC 7-CH 28TSSOP |
| 标准包装： | 50 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 7 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 管件 |
| 配用： | EVAL-ADM1060EBZ-ND - BOARD EVALUATION ADM1060 |
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ADM1060
PROGRAMMING
CONFIGURATION DOWNLOAD AT POWER-UP
The configuration of the ADM1060—the UV/OV thresholds,
glitch filter timeouts, PLB combinations, PDO pull-ups, etc.—is
dictated by the contents of the RAM. The RAM is comprised of
local latches that set the configuration. These latches are double
buffered and are actually comprised of two identical latches
(Latch A and Latch B). An update of the double-buffered latch
updates Latch A first and then Latch B. The advantage of this
architecture is explained below. These latches are volatile
memory and lose their contents at power-down. Therefore, at
power-up the configuration in the RAM must be restored. This
is achieved by downloading the contents of the EEPROM
(nonvolatile memory) to the local latches. This download
occurs in a number of steps.
1. With no power applied to the device, the PDOs are all high
impedance.
2. Once 1 V appears on any of the inputs connected to the V DD
arbitrator (VH or VPn), the PDOs are all (weakly) pulled to
GND.
3. Once the supply rises above the undervoltage lockout of the
device (UVLO is 2.5 V), the EEPROM starts to download to
the RAM.
4. The EEPROM downloads its contents to all Latch As.
5. Once the contents of the EEPROM are completely
downloaded, the device controller outputs a control pulse
enabling all Latch As to download to all Latch Bs, thus com-
pleting the configuration download. Any attempt to
communicate with the device prior to this download comple-
tion will result in a NACK being issued from the ADM1060.
UPDATING THE CONFIGURATION
Once the device is powered up with all of the configuration
settings loaded from EEPROM into the RAM registers, the user
may wish to alter the configuration of functions on the
ADM1060; for example, change the UV or OV limit of an SFD,
the fault output of an SFD, the timeout of the watchdog detec-
tor, the rise time delay of one of the PDOs, and so on.
The ADM1060 provides a number of options that allow the user
to update the configuration differently over the SMBus inter-
face. All of these options are controlled in the register UPDCFG.
The options are
1. Update the configuration in real time. The user writes to
RAM across the SMBus and the configuration is updated
immediately.
2. Update the A Latches “offline” and then update all B Latches
at the same time. With this method, the configuration of the
ADM1060 will remain unchanged and continue to operate in
the original setup until the instruction is given to update the
B Latches.
3. Change EEPROM register contents offline and then
download the revised EEPROM contents to the RAM regis-
ters. Again, with this method, the configuration of the
ADM1060 will remain unchanged and continue to operate in
the original setup until the instruction is given to change.
The instruction to download from the EEPROM in option 3
above is also a useful way to restore the original EEPROM con-
tents if revisions to the configuration are unsatisfactory and the
user wants the ADM1060 to return to a known operating mode.
This type of operation is possible because of the topology of the
ADM1060. The local (volatile) registers, or RAM, are all double-
buffered latches. Setting Bit 0 of the UPDCFG register to 1
leaves the double-buffered latches open at all times. If Bit 0 is set
to 0, then when RAM write occurs across the SMBus only the
first side of the double-buffered latch is written to. The user
must then write a 1 to Bit 1 of the UPDCFG register. This gen-
erates a pulse to update all of the second latches at once.
EPROM writes work similarly.
A final bit in this register is used to enable EEPROM page
erasure. If this bit is set high, the contents of an EEPROM page
can all be set to 0. If low, the contents of a page cannot be
erased, even if the command code for page erasure is
programmed across the SMBus.
The bit map for register UPDCFG is shown in Table 56. A flow
chart for download at power-up and subsequent configuration
Rev. B | Page 40 of 52
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADM1060ARUCS0001R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0100R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0101R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0102R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0103R7 | 制造商:Analog Devices 功能描述: |
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