参数资料
| 型号： | ADM1060ARU |
| 厂商： | Analog Devices Inc |
| 文件页数： | 31/52页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVIS/SEQUENC 7-CH 28TSSOP |
| 标准包装： | 50 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 7 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 管件 |
| 配用： | EVAL-ADM1060EBZ-ND - BOARD EVALUATION ADM1060 |
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ADM1060
PROGRAMMABLE DELAY BLOCK
Each output of the PLBA is fed into a separate programmable
delay block (PDB). The PDB enables the user to add a delay to
PROGRAMMED RISE TIME
PDB INPUT
PROGRAMMED RISE TIME
PROGRAMMED
FALL TIME = 0
the logic block output before it is applied to either a PDO or one
of the other PLBs (the output of a PLB can be the input to any
of the other PLBs, but not itself). The PDB operation is similar
to that of the glitch filter (discussed in the SFD section). There
is an important difference between the two functions, however.
The delay on the falling edge of an input to the PDB can be
t 0
t RISE
t 0
t RISE t FALL
programmed independently of the rising edge. This allows the
user to program the length of the pulse output from the PDB.
Thus, for instance, the width of the pulse from the watchdog
fault detector can be adjusted, or the user can ensure that a sup-
ply supervised by one of the SFDs is within its UV/OV range
for a programmed period of time before asserting a PDO. A
t 0
t RISE
PDB OUTPUT
t 0
t RISE t FALL
delay of 0 ms to 500 ms can be programmed in the PnPDBTIM
registers. Four bits each are used to program the rising edge and
falling edge.
PROGRAMMING RISE TIME ONLY
PDB INPUT
PROGRAMMED
PROGRAMMED
PROGRAMMED PROGRAMMED
Once programmed, the PDB operates as follows. If the user
RISE TIME
FALL TIME
RISE TIME
FALL TIME
programs a delay on the rising edge of, say, 200 ms, the PDB
looks for a rising edge on the input. Once it sees the edge it
starts a timer. If the input remains high and the timer reaches
200 ms, the PDB immediately outputs a rising edge. If the input
falls low before the timer has reached 200 ms, no edge is output
from the PDB and the timer is reset. Because there is separate
t 0
t RISE
t 1
t FALL
t 0
t RISE
t 1
t FALL
control over the falling edge, if no delay is programmed on the
falling edge, the delay defaults to 0 ms and a falling edge on the
input will immediately appear on the output. If a falling edge
delay is programmed, the PDB operates exactly the opposite as
it does for a rising edge. Again, if a delay of, say, 200 ms is pro-
grammed on the falling edge, the PDB looks for a falling edge
t 0
t RISE
t 1
t FALL
PDB OUTPUT
t 0
t RISE
t 1
t FALL
on the input. Once it sees the edge, it starts a timer. If the input
remains low and the timer reaches 200 ms, the output transi-
tions from high to low. A valid rising edge must appear at the
output before a falling edge delay can be activated. The function
Aside from the extra timing flexibility, the programmable delay
also provides a crude form of filtering. In much the same way as
the glitch filter operates, an input must be high (or low) for a
programmed period of time before being seen on the output.
Transients that are shorter than the programmed timeouts will
not appear on the output. The bit map for the register that con-
Rev. B | Page 31 of 52
PROGRAMMING RISE TIME AND FALL TIME
Figure 22. Programmable Delay Block (PDB) Functionality
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADM1060ARUCS0001R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0100R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0101R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0102R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0103R7 | 制造商:Analog Devices 功能描述: |
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