参数资料
| 型号： | ADM1060ARU |
| 厂商： | Analog Devices Inc |
| 文件页数： | 41/52页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVIS/SEQUENC 7-CH 28TSSOP |
| 标准包装： | 50 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 7 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 管件 |
| 配用： | EVAL-ADM1060EBZ-ND - BOARD EVALUATION ADM1060 |
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ADM1060
Table 55. List of Configuration Update Registers
Default Power-
Hex Addr.
90
Table
Name
UPDCFG
On Value
0x00
Description
Configuration Update Control register for changing configuration of the
ADM1060 after power-up
Table 56. Bit Map for UPDCFG Register 0x90 (Power-On Default 0x00)
Bit
7–4
3
2
Name
Reserved
EE_ERASE
EEPROMLD
R/W
N/A
R/W
W
Description
Cannot be used
If set high, EEPROM page erasure can be programmed.
If set high, the ADM1060 will download the contents of its EEPROM to the RAM registers. This bit
self-clears (returns to 0) after the download.
1
RAMLD
W
If set high, the ADM1060 will download the buffered RAM register data into the local latches. This bit
self-clears (returns to 0) after the download.
0
UPD
R/W
If set high, the ADM1060 will update its configuration in real time as a word is written to a local RAM
register via the SMBus.
SMBus
DEVICE
CONTROLLER
POWER-UP
(V CC >2.5V)
EEPROMLD
DATA
RAMLD
UPD
FUNCTION (E.G.,
EEPROM
LATCH A
LATCH B
OV THRESHOLD
ON VP1)
Figure 24. Configuration Update Flow Diagram
INTERNAL REGISTERS
The ADM1060 contains a large number of data registers. A brief
description of the principal registers is given below. More
detailed descriptions are given in the relevant sections of this
data sheet.
Address Pointer Register. This register contains the address
that selects one of the other internal registers. When writing to
the ADM1060, the first byte of data is always a register address,
Configuration Registers. These registers provide control and
configuration for various operating parameters of the
ADM1060.
Polarity Registers. These registers define the polarity of inputs
to the PLBA.
Mask Registers. These registers allow masking of individual
inputs to the PLBA and masking of faults in the fault reporting
registers.
which is written to the Address Pointer register.
Rev. B | Page 41 of 52
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| ADM1060ARUCS0001R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
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| ADM1060ARUCS0101R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0102R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
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