参数资料
| 型号： | ADM1060ARU |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/52页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVIS/SEQUENC 7-CH 28TSSOP |
| 标准包装： | 50 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 7 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 管件 |
| 配用： | EVAL-ADM1060EBZ-ND - BOARD EVALUATION ADM1060 |
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ADM1060
GENERAL-PURPOSE INPUTS (GPIs)
The ADM1060 has four general-purpose logic inputs (GPIs).
These are TTL/CMOS logic level compatible. Standard logic
signals can be applied to the pins: RESET from reset generators,
PWRGOOD signals, fault flags, manual resets, and so on. These
signals can be gated with the other inputs supervised by the
ADM1060 and used to control the status of the PDOs. The
inputs can be simply buffered, or a logic transition can be
detected and a pulse output generated. The width of this pulse is
programmable from 10 μs to a maximum of 10 ms. The
configuration of the GPIs is shown in the register and bit maps
below.
The GPIs also feature a glitch filter similar to that provided on
the SFDs. This enables the user to ignore spurious transitions
on the GPIs. For example, the glitch filter can be used to
Table 22. General-Purpose Inputs (GPIn) Registers
debounce a manual reset switch. The length of the glitch filter
can also be programmed.
LOGIC STATE OF THE GPIs AND OTHER LOGIC
INPUTS
Each of the GPIs can have a weak (10 μA) pull-down current
source. The current sources can be connected to the inputs by
progamming the relevant bit in the PDEN register. This enables
the user to control the condition of these inputs, pulling them to
GND even when they are unused or left floating.
Note that the same pull-down function is provided for the
SMBus address pins, A0 and A1, and for the WDI pin. A register
is used to program which of the inputs is connected to the cur-
rent sources.
Hex Address
98
Name
GPI4CFG
Default Power-On Value
0x00
Description
GPI4 configuration setup of the glitch filter delay, pulse width,
level/edge detection, etc.
99
GPI3CFG
0x00
GPI3 configuration setup of the glitch filter delay, pulse width,
level/edge detection, etc.
9A
GPI2CFG
0x00
GPI2 configuration setup of the glitch filter delay, pulse width,
level/edge detection, etc.
9B
GPI1CFG
0x00
GPI1 configuration setup of the glitch filter delay, pulse width,
level/edge detection, etc.
Table 23. GPInCFG Registers Bit Map (Power-On Default 0x00)
Bit
7
6
Name
Reserved
INVIN
R/W
N/A
R/W
Description
Cannot Be Used
If High, Invert Input
5
INTYP
R/W
Determines whether a Level or an Edge is Detected on
INTYP
Detect
the Pin. If an edge is detected, a positive pulse of
programmable length is output.
0
1
Detect Level
Detect Edge
4–3
PULS1?0
R/W
Length of Pulse Output Once an Edge Has Been
PULS1
PULS0 Pulse Length Selected (μs)
Detected on Input
0
0
1
1
0 10
1 100
0 1,000
1 10,000
2–0
GF2?GF0
R/W
Length of Time for which the Input Is Ignored
GF2
GF1 GF0
Glitch Filter
Delay (μs)
Rev. B | Page 19 of 52
0
0
0
0
1
1
1
1
0 0 0
0 1 5
1 0 10
1 1 20
0 0 30
0 1 50
1 0 75
1 1 100
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