参数资料
| 型号： | ADM1060ARU |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/52页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVIS/SEQUENC 7-CH 28TSSOP |
| 标准包装： | 50 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 7 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 管件 |
| 配用： | EVAL-ADM1060EBZ-ND - BOARD EVALUATION ADM1060 |
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ADM1060
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DIGITAL INPUTS (GPI 1–4, WDI, A0, A1) 4
Input High Voltage, V IH
Input Low Voltage, V IL
2.0
0.8
V
V
Input High Current, I IH
Input Low Current, I IL
Input Capacitance
Programmable Pull-Down Current, I PULLDOWN
–1
10
10
1
μA
μA
pF
μA
V IN = 5.5 V
V IN = 0 V
If known logic state required
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, V IH
Input Low Voltage, V IL
2.0
0.8
V
V
Output Low Voltage, V OL
0.4
V
I OUT = ?3.0 mA
PROGRAMMABLE DELAY BLOCK
Timeout
0
500
ms
16 programmable options on both rising and
falling edge
WATCHDOG TIMER INPUT
Timeout
0
12.8
s
Eight programmable timeout options
EEPROM RELIABILITY
Endurance 5, 6
Data Retention 7
SERIAL BUS TIMING 8
100
10
Kcycles
Years
Clock Frequency, f SCLK
Glitch Immunity, t SW
Bus Free Time, t BUF
Start Setup Time, t SU;STA
Start Hold Time, t HD;STA
SCL Low Time, t LOW
SCL High Time, t HIGH
SCL, SDA Rise Time, t r
SCL, SDA Fall Time, t f
Data Setup Time, t SU;DAT
Data Hold Time, t HD;DAT
4.7
4.7
4
4.7
4
250
300
400
50
1000
300
kHz
ns
μs
μs
μs
μs
μs
ns
μs
ns
ns
At least one VPn must be ≥3.0 V if used as supply. VH must be ≥4.5 V if used as supply.
Specification is not production tested, but is supported by characterization data at initial product release.
1% threshold accuracy is only achievable on parts preprogrammed by Analog Devices. Contact ADM1060.program@analog.com for further details.
Logic inputs will accept input high voltages up to 5.5 V even when the device is operating at supply voltages below 5 V.
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at ?40°C, +25°C, and +85°C.
For programming and erasing of EEPROM, a minimum V DD = 3.0 V is required 0°C to +85°C and a minimum V DD = 4.5 V is required ?40°C to 0°C.
Retention lifetime equivalent at junction temperature (T J ) = 55°C as per JEDEC Std. 22 method A117.
Timing specifications are tested at logic levels of V IL = 0.8 V for a falling edge and V IH = 2.0 V for a rising edge.
NOTES
1
2
3
4
5
6
7
8
Rev. B | Page 6 of 52
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