参数资料
| 型号： | ADM1060ARU |
| 厂商： | Analog Devices Inc |
| 文件页数： | 36/52页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVIS/SEQUENC 7-CH 28TSSOP |
| 标准包装： | 50 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 7 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 管件 |
| 配用： | EVAL-ADM1060EBZ-ND - BOARD EVALUATION ADM1060 |
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ADM1060
The functionality of the fault plane is best illustrated with an
example. For instance, take VP1 to have an input supply of 5.0 V.
A UV/OV window of 4.5 V to 5.5 V is set up on VP1. The
supply is ramped in and out of this window, each time reading
the contents of LATF1 and LATF2. The values recorded are as
follows:
1. VP1 at 5 V: LATF1 = LATF2 = 00000000. This is expected.
The supply is in tolerance, SFD output is 0, therefore no fault.
2. VP1 at 4.2 V: LATF1 = 10001000, LATF2 = 00000000. SFD
output has changed status to 1, therefore ANYFLT goes high.
3. VP1 at 5.0 V: LATF1 = 10000000, LATF2 = 00000000. SFD
output has changed status to 0, therefore ANYFLT goes high
again.
4. VP1 at 5.8 V: LATF1 = 10001000, LATF2 = 00000000. SFD
output again changed status from 0 to 1, so ANYFLT goes
high.
Table 42. Status Registers
5. VP1 at 4.2 V: LATF1 = 10000000, LATF2 = 00000000. At first
glance, this would appear to be incorrect since the SFD out-
put should be at 1 (4.2 V is an undervoltage fault). However,
in ramping down from 5.8 V to 4.2 V, the supply passed into
the UV/OV window, the SFD output changed status from 1 to
0, ANYFLT was set high, and the register contents were
latched. It is these values that were read, before being reset by
reading LATF2.
There are also two mask registers provided that enable the user
to ignore a fault on a given function. The bits of the error mask
registers are mapped in the same way as those of the fault regis-
ters with the exception that the ANYFLT bit cannot be masked.
Setting a 1 in the error mask register results in the equivalent bit
in the fault register always remaining at 0, regardless of whether
there is a fault on that function or not. The register and bit maps
for both the fault and error mask registers are shown below.
Hex Addr.
D8
D9
DA
DB
DE
DF
Table
Table 45
Name
UVSTAT
OVSTAT
SFDSTAT
GWSTAT
PDOSTAT1
PDOSTAT2
Default Power-On Value
0x00
0x00
0x00
0x00
0x00
0x00
Description
Logic output of the UV comparator on each of the seven SFDs
Logic output of the OV comparator on each of the seven SFDs
Logic output (post Fault Type block) on each of the seven SFDs
Logic state of the four GPIs and the Watchdog Fault Detector
Logic output of PDOs 1 to 8
Logic output of PDO 9
Table 43. Bit Map for UVSTAT Register 0xD8 (Power-On Default 0x00)
Bit
7
6
5
4
3
2
1
0
Name
Reserved
VP4UV
VP3UV
VP2UV
VP1UV
VHUV
VB2UV
VB1UV
R/W
N/A
R
R
R
R
R
R
R
Description
Cannot Be Used
If high, voltage on VP4 input is lower than the UV threshold.
If high, voltage on VP3 input is lower than the UV threshold.
If high, voltage on VP2 input is lower than the UV threshold.
If high, voltage on VP1 input is lower than the UV threshold.
If high, voltage on VH input is lower than the UV threshold.
If high, voltage on VB2 input is lower than the UV threshold.
If high, voltage on VB1 input is lower than the UV threshold.
Rev. B | Page 36 of 52
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相关代理商/技术参数 |
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| ADM1060ARUCS0001R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0100R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0101R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0102R7 | 功能描述:IC SUPERVISOR/SEQUENCER 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| ADM1060ARUCS0103R7 | 制造商:Analog Devices 功能描述: |
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