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| 型号： | ADP1043A-USB-Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/72页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD DIG POWER SUPPLY |
| 标准包装： | 1 |
| 附件类型： | 连接 USB 至 I2C 的接收器 |
| 适用于相关产品： | ADP1043A |
| 相关产品： | ADP1043AACPZ-RLDKR-ND - IC SECONDARY SIDE CTRLR 32LFCSP ADP1043AACPZ-RLCT-ND - IC SECONDARY SIDE CTRLR 32LFCSP ADP1043AACPZ-RLTR-ND - IC SECONDARY SIDE CTRLR 32LFCSP |
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ADP1043A
VOLTAGE SENSE AND CONTROL LOOP
Multiple voltage sense inputs on the ADP1043A are used for the
monitoring, control, and protection of the power supply output.
The voltage information is available through the I 2 C interface.
All voltage sense points can be calibrated digitally to remove
any errors due to external components. This calibration can be
performed in the production environment, and the settings can
be stored in the EEPROM of the ADP1043A (see the Power
The update rate of the ADC from a control loop standpoint
is set to the switching frequency. Therefore, if the switching
frequency is set to 100 kHz, the ADC outputs a signal every
100 kHz to the control loop. Because the Σ-Δ modulators of the
ADC sample at 1.6 MHz, the output of the ADC is the average
of the 16 readings taken during the 1.6 MHz time frame.
For voltage monitoring, the VS1, VS2, and VS3 voltage value
registers are updated every 10 ms. The ADP1043A stores every
ADC sample for 10 ms and then outputs the average value at the
end of the 10 ms period. Therefore, if these registers are read at
least every 10 ms, a true average value is read. The same applies
to the CS1 and CS2 current readings.
For the control loop, the high speed signal always comes from
the VS1 high speed ADC. The low speed signal normally comes
from the VS3 low speed ADC. However, during soft start or in
response to a load OVP or other fault condition, the ADP1043A
can switch its low speed regulating point from VS3 to VS1.
VS1 Operation (VS1)
VS1 is used for the monitoring and protection of the power
supply voltage at the output of the LC stage, upstream of the
OrFET. This is also the high frequency feedback loop for the
power supply. The VS1 sense point on the power rail needs an
external resistor divider to bring the nominal common-mode
signal to 1 V at the VS1 pin (see Figure 13). The resistor divider
is necessary because the ADP1043A VS1 ADC input range is
0 V to 1.55 V. This divided-down signal is internally fed into a
high speed and a low speed Σ-Δ ADC. The output of the VS1
ADCs goes to the digital filter.
The high speed ADC has a 2 MHz bandwidth and is run from
a 25 MHz clock. It has a range of ±18 mV. When the sampling
rate is 200 kHz, there is 0.6 mV (two LSBs) of quantization noise.
Increasing the sampling rate to 400 kHz increases the quanti-
zation noise to 1.2 mV.
In the event of a load overvoltage condition, the power supply
is regulated from the VS1 sense point, rather than from the
VS3 sense point.
VS2 Operation (VS2)
VS2 is typically used for the monitoring and protection of the
output of the power supply, downstream of the OrFET. It is
used with VS1 to control the OrFET gate drive turn-on. The
VS2 sense point on the power rail needs an external resistor
divider to bring the nominal common-mode signal to 1 V at
the VS2 pin (see Figure 13). The resistor divider is necessary
12V
12V
12V
because the ADP1043A VS2 ADC input range is 0 V to 1.55 V.
This divided-down signal is internally fed into an ADC. The
LOAD
output of the VS2 ADC goes to the VS2 voltage value register
(Register 0x16).
1V
11k ?
1k ?
1V
11k ?
1k ?
VS3 Operation (VS3+, VS3?)
VS3± is used for the monitoring and protection of the remote
load voltage. It is a fully differential input. This is the main
PGND
VS1
VS2
VS3+
VS3–
11k ?
1V
1k ?
feedback sense point for the power supply control loop. The
VS3 sense point on the power rail needs an external resistor
divider to bring the nominal common-mode signal to 1 V at
the VS3± pins (see Figure 13). The resistor divider is necessary
VS1
HIGH ADC
SPEED
6 BITS
VS1
LOW ADC
SPEED
12 BITS
VS2 ADC
12 BITS
VS3 ADC
12 BITS
because the ADP1043A VS3 ADC input range is 0 V to 1.55 V.
This divided-down signal is internally fed into an ADC. The
output of the VS3 ADC goes to the digital filter.
HIGH
FREQUENCY
ADCs
FEEDBACK
LOOP
DIGITAL
FILTER
LOW FREQUENCY
FEEDBACK LOOP
The ADP1043A includes several ADCs. The high speed ADC is
described in the VS1 Operation (VS1) section. The other ADCs
are low speed, high resolution. They have a 1 kHz bandwidth
and 12-bit resolution. Each ADC has its own voltage reference
Figure 13. Voltage Sense Configuration
for added protection from potential failure. The digital output
of each ADC is readable through the appropriate value register.
Rev. 0 | Page 13 of 72
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