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参数资料
| 型号： | ADP1043A-USB-Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 33/72页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD DIG POWER SUPPLY |
| 标准包装： | 1 |
| 附件类型： | 连接 USB 至 I2C 的接收器 |
| 适用于相关产品： | ADP1043A |
| 相关产品： | ADP1043AACPZ-RLDKR-ND - IC SECONDARY SIDE CTRLR 32LFCSP ADP1043AACPZ-RLCT-ND - IC SECONDARY SIDE CTRLR 32LFCSP ADP1043AACPZ-RLTR-ND - IC SECONDARY SIDE CTRLR 32LFCSP |
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ADP1043A
REGISTER LISTING
Table 7. Register List
Address
Name
Address
Name
Fault Registers
Voltage Sense Registers
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
Fault Register 1
Fault Register 2
Fault Register 3
Fault Register 4
Latched Fault Register 1
Latched Fault Register 2
Latched Fault Register 3
Latched Fault Register 4
Fault Configuration Register 1
Fault Configuration Register 2
0x31
0x32
0x33
0x34
0x35
0x36
0x38
0x39
0x3A
0x3B
VS3 voltage setting (remote voltage)
VS1 overvoltage limit (OVP)
VS2 and VS3 overvoltage limit (OVP)
VS1 undervoltage limit (UVP)
Line impedance limit
Load line impedance
VS1 trim
VS2 trim
VS3 trim
Light load mode disable setting
0x0A
Fault Configuration Register 3
ID Registers
0x0B
0x0C
0x0D
Fault Configuration Register 4
Fault Configuration Register 5
Fault Configuration Register 6
0x3C
0x3D
0x3E
Silicon revision ID
Manufacturer ID
Device ID
0x0E
Flag configuration
PWM and Synchronous Rectification Timing Registers
0x0F
Soft start blank fault flags
0x3F
OUTAUX switching frequency setting
Value Registers
0x40
PWM switching frequency setting
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1D
0x1E
0x1F
0x20
First flag ID
Reserved
VS1/PWM value (input voltage)
CS1 value (input current)
CS1 × (VS1/PWM) value (input power)
VS1 voltage value
VS2 voltage value
VS3 voltage value (output voltage)
CS2 value (output current)
CS2 × VS3 value (output power)
RTD temperature value
Share bus value
Modulation value
Line impedance value
Reserved
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
OUTA rising edge timing (OUTA pin)
OUTA rising edge setting (OUTA pin)
OUTA falling edge timing (OUTA pin)
OUTA falling edge setting (OUTA pin)
OUTB rising edge timing (OUTB pin)
OUTB rising edge setting (OUTB pin)
OUTB falling edge timing (OUTB pin)
OUTB falling edge setting (OUTB pin)
OUTC rising edge timing (OUTC pin)
OUTC rising edge setting (OUTC pin)
OUTC falling edge timing (OUTC pin)
OUTC falling edge setting (OUTC pin)
OUTD rising edge timing (OUTD pin)
OUTD rising edge setting (OUTD pin)
OUTD falling edge timing (OUTD pin)
Current Sense and Current Limit Registers
0x50
OUTD falling edge setting (OUTD pin)
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
CS1 gain trim
CS1 accurate OCP limit
CS2 gain trim
CS2 analog offset trim
CS2 digital trim
CS2 accurate OCP limit
CS1 fast OCP setting
Volt-second balance gain setting
Share bus bandwidth
Share bus setting
Temperature gain trim
PSON/soft start setting
Pin polarity setting
Modulation limit
OTP threshold
OrFET
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
SR1 rising edge timing (SR1 pin)
SR1 rising edge setting (SR1 pin)
SR1 falling edge timing (SR1 pin)
SR1 falling edge setting (SR1 pin)
SR2 rising edge timing (SR2 pin)
SR2 rising edge setting (SR2 pin)
SR2 falling edge timing (SR2 pin)
SR2 falling edge setting (SR2 pin)
OUTAUX rising edge timing (OUTAUX pin)
OUTAUX rising edge setting (OUTAUX pin)
OUTAUX falling edge timing (OUTAUX pin)
OUTAUX falling edge setting (OUTAUX pin)
OUTx and SRx pin disable setting
Password lock
Rev. 0 | Page 33 of 72
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