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| 型号： | ADP1043A-USB-Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 41/72页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD DIG POWER SUPPLY |
| 标准包装： | 1 |
| 附件类型： | 连接 USB 至 I2C 的接收器 |
| 适用于相关产品： | ADP1043A |
| 相关产品： | ADP1043AACPZ-RLDKR-ND - IC SECONDARY SIDE CTRLR 32LFCSP ADP1043AACPZ-RLCT-ND - IC SECONDARY SIDE CTRLR 32LFCSP ADP1043AACPZ-RLTR-ND - IC SECONDARY SIDE CTRLR 32LFCSP |
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ADP1043A
CURRENT SENSE AND CURRENT LIMIT REGISTERS
Table 29. Register 0x21—CS1 Gain Trim
Bits
7
Name
Gain polarity
R/W
R/W
Description
1 = negative gain is introduced.
0 = positive gain is introduced.
[6:0]
CS1 gain trim
R/W
This value calibrates the primary side current sense gain. See the CS1 Trim section for more
information.
Table 30. Register 0x22—CS1 Accurate OC P Limit
Bits
[7:5]
Name
CS1 fast OCP blanking
R/W
R/W
Description
These bits determine the blanking time for CS1 before fast OCP is enabled. This time is measured
from the start of a switching cycle. It is synchronized with the rising edge of OUTB and OUTD. If
using OUTAUX, the time is synchronized with the rising edge of OUTAUX.
Bit 7
0
0
0
0
1
1
1
1
Bit 6
0
0
1
1
0
0
1
1
Bit 5
0
1
0
1
0
1
0
1
Delay (ns)
0
40
80
120
200
400
600
800
[4:0]
CS1 accurate OCP
R/W
These bits set the CS1 accurate OCP threshold. The digital word that is output from the CS1
ADC is compared with this threshold. If the CS1 ADC reading (Register 0x13) is greater than
the OCP threshold set by these bits, the CS1 accurate OCP flag is set. This value should be
programmed only after the CS1 trim has been performed. The range of these bits is from
0 to 31, that is, 0 V to 1.38 V in 43.125 mV steps.
The following equation gives the threshold of the CS1 OCP:
CS1_OCP_Threshold = ( CS1_OCP_Limit /31) × 1.38
The range is programmable from 0% to 138% of the nominal voltage on the CS1 pin.
For example, if the CS1 OCP limit is 12 V, then
CS1_OCP_Threshold = (12/31) × 1.38 V = 534 mV
Setting these bits to 0 gives an OCP limit of 0% of the nominal voltage on the CS1 pin.
Setting these bits to 10 gives an OCP limit of 44.5% of the nominal voltage on the CS1 pin.
Setting these bits to 31 gives an OCP limit of 138% of the nominal voltage on the CS1 pin.
Table 31. Register 0x23—CS2 Gain Trim
Bits
[7:6]
Name
CS2 nominal
R/W
R/W
Description
These bits set the nominal full-scale voltage drop across the sense resistor. This is Step 1 in
the CS2 Offset Trim section. These bits set the LSB step size of the CS2 ADC.
Nominal Voltage Drop
Bit 7
0
0
1
Bit 6
0
1
0
Across R SENSE at Full Scale (mV)
37.5
75
150
LSB Step Size (μV)
15.26
30.52
61.04
5
Gain polarity
R/W
1 = negative gain is introduced.
0 = positive gain is introduced.
[4:0]
CS2 gain trim
R/W
This register calibrates the secondary side (CS2) current sense gain. It calibrates for errors in
the sense resistor. This is Step 2 in the CS2 Gain Trim section.
Rev. 0 | Page 41 of 72
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