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| 型号： | ADP1043A-USB-Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/72页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD DIG POWER SUPPLY |
| 标准包装： | 1 |
| 附件类型： | 连接 USB 至 I2C 的接收器 |
| 适用于相关产品： | ADP1043A |
| 相关产品： | ADP1043AACPZ-RLDKR-ND - IC SECONDARY SIDE CTRLR 32LFCSP ADP1043AACPZ-RLCT-ND - IC SECONDARY SIDE CTRLR 32LFCSP ADP1043AACPZ-RLTR-ND - IC SECONDARY SIDE CTRLR 32LFCSP |
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ADP1043A
SOFT START
A dedicated filter is used during soft start. The filter is disabled
at the end of the soft start routine, and the voltage loop digital
filter is used.
Fault Condition During Soft Start
If a CS1 fast OCP fault condition occurs during soft start, the
entire soft start routine is reset, and the ADP1043A begins another
soft start routine. All other fault flags are ignored during soft start.
Soft Start Routine
When the user turns on the power supply (enables PSON), the
following soft start procedure occurs:
3.
4.
5.
6.
The soft start begins to ramp up the power supply voltage
at the start of Time t 2 .
The ADP1043A keeps the OrFET gate signal turned off.
The voltage differential across the OrFET increases (VS1 ?
VS2) due to the diode conduction of the OrFET. When the
voltage differential reaches the OrFET enable threshold
(Register 0x30, Bits[5:4]), the OrFET gate signal is enabled
at Time t 3 . The ADP1043A begins to regulate voltage from
VS3 instead of VS1.
After the power supply voltage increases above the VS1 UVP
undervoltage limit (Register 0x34, Bits[6:0]), at the end of
Time t 4 , the UVP flag is reset.
After the UVP flag is reset and if all other PGOOD1 fault
1.
2.
The PSON signal is enabled at Time t 0 . The ADP1043A
checks that initial flags are OK. These flags include VDD
OK and GND OK.
The ADP1043A waits for Time t 1 before it begins soft start.
The length of t 1 is set in Register 0x2C, Bits[4:3].
t 0
conditions are OK, the PGOOD1 signal waits for Time t 5
before it is enabled. The length of t 5 is programmable in
Register 0x2D, Bits[7:4].
t 3
t 1
t 2
t 4
t 5
PSON
SOFT START RAMP
UVP
V OUT VOLTAGE
120mV
(VS1 – VS2) VOLTAGE
GATE SIGNAL
LOOP CONTROLLED FROM VS1
LOOP CONTROLLED FROM VS3
UVP FLAG
PGOOD1
Figure 21. Soft Start Timing Diagram
Rev. 0 | Page 19 of 72
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADP1043-EVALZ | 制造商:Analog Devices 功能描述:EVALUATION BOARDS - Bulk |
| ADP1043FB100-EVALZ | 制造商:Analog Devices 功能描述:ADP1043 100W EVALUATION BOARD |
| ADP1045ACPZ-RL | 制造商:Analog Devices 功能描述: |
| ADP1046 | 制造商:AD 制造商全称:Analog Devices 功能描述:Digital Controller for Isolated |
| ADP1046-100-EVALZ | 功能描述:BOARD EVAL FOR ADP1046-100 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PCI Express® (PCIe) 主要目的:接口，收发器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要属性:- 次要属性:- 已供物品:板 |
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