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| 型号： | ADP1043A-USB-Z |
| 厂商： | Analog Devices Inc |
| 文件页数： | 54/72页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD DIG POWER SUPPLY |
| 标准包装： | 1 |
| 附件类型： | 连接 USB 至 I2C 的接收器 |
| 适用于相关产品： | ADP1043A |
| 相关产品： | ADP1043AACPZ-RLDKR-ND - IC SECONDARY SIDE CTRLR 32LFCSP ADP1043AACPZ-RLCT-ND - IC SECONDARY SIDE CTRLR 32LFCSP ADP1043AACPZ-RLTR-ND - IC SECONDARY SIDE CTRLR 32LFCSP |
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ADP1043A
Table 66. Register 0x47—OUTB Falling Edge Timing (OUTB Pin)
Bits
[7:0]
Name
t 4
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 4 time. This value is always used with
the top four bits of Register 0x48, which contains the four LSBs of the t 4 time. Each LSB
corresponds to 5 ns resolution.
Table 67. Register 0x48—OUTB Falling Edge Setting (OUTB Pin)
Bits
[7:4]
Name
t 4
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 4 time. This value is always used with the eight
bits of Register 0x47, which contains the eight MSBs of the t 4 time. Each LSB corresponds to
5 ns resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 4 edge.
0 = no PWM modulation of the t 4 edge.
2
t 4 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 4 right.
0 = positive sign. Increase of PWM modulation moves t 4 left.
[1:0]
Reserved
R/W
Reserved. These bits should be set to 00 for normal operation.
Table 68. Register 0x49—OUTC Rising Edge Timing (OUTC Pin)
Bits
[7:0]
Name
t 5
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 5 time. This value is always used with
the top four bits of Register 0x4A, which contains the four LSBs of the t 5 time. Each LSB
corresponds to 5 ns resolution.
Table 69. Register 0x4A—OUTC Rising Edge Setting (OUTC Pin)
Bits
[7:4]
Name
t 5
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 5 time. This value is always used with the eight
bits of Register 0x49, which contains the eight MSBs of the t 5 time. Each LSB corresponds to
5 ns resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 5 edge.
0 = no PWM modulation of the t 5 edge.
2
t 5 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 5 right.
0 = positive sign. Increase of PWM modulation moves t 5 left.
[1:0]
Reserved
R/W
Reserved. These bits should be set to 00 for normal operation.
Table 70. Register 0x4B—OUTC Falling Edge Timing (OUTC Pin)
Bits
[7:0]
Name
t 6
R/W
R/W
Description
This register contains the eight MSBs of the 12-bit t 6 time. This value is always used with
the top four bits of Register 0x4C, which contains the four LSBs of the t 6 time. Each LSB
corresponds to 5 ns resolution.
Table 71. Register 0x4C—OUTC Falling Edge Setting (OUTC Pin)
Bits
[7:4]
Name
t 6
R/W
R/W
Description
These bits contain the four LSBs of the 12-bit t 6 time. This value is always used with the eight
bits of Register 0x4B, which contains the eight MSBs of the t 6 time. Each LSB corresponds to
5 ns resolution.
3
Modulate enable
R/W
1 = PWM modulation acts on the t 6 edge.
0 = no PWM modulation of the t 6 edge.
2
t 6 sign
R/W
1 = negative sign. Increase of PWM modulation moves t 6 right.
0 = positive sign. Increase of PWM modulation moves t 6 left.
[1:0]
Reserved
R/W
Reserved. These bits should be set to 00 for normal operation.
Rev. 0 | Page 54 of 72
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