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参数资料
| 型号： | ADSP-21160MKB-80 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 39/52页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 400 BGA |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 80MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 512kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 2.50V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 400-BBGA |
| 供应商设备封装： | 400-PBGA（27x27） |
| 包装： | 托盘 |
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ADSP-21160M
–44–
REV. 0
Example: Estimate P
EXT with the following assumptions:
A system with one bank of external data memory—asyn-
chronous RAM (64-bit)
Four 64K × 16 RAM chips are used, each with a load of
10 pF
External data memory writes occur every other cycle, a
rate of 1/(4 t
CK), with 50% of the pins switching
The bus cycle time is 40 MHz (t
CK = 25 ns).
The P
EXT equation is calculated for each class of pins that
can drive:
A typical power consumption can now be calculated for
these conditions by adding a typical internal power
dissipation:
P
TOTAL = PEXT + PINT + PPLL
Where:
P
EXT is from Table 30
P
INT is IDDINT × 2.5V, using the calculation IDDINT listed in
P
PLL is AIDD × 2.5V, using the value for AIDD listed in
Note that the conditions causing a worst-case P
EXT are
different from those causing a worst-case P
INT. Maximum
P
INT cannot occur while 100% of the output pins are
switching from all ones to all zeros. Note also that it is not
common for an application to have 100% or even 50% of
the outputs switching simultaneously.
Test Conditions
The test conditions for timing parameters appearing in
ADSP-21160M specifications on page 13 include output
disable time, output enable time, and capacitive loading.
Output Disable Time
Output pins are considered to be disabled when they stop
driving, go into a high impedance state, and start to decay
from their output high or low voltage. The time for the
voltage on the bus to decay by –V is dependent on the capac-
itive load, C
L and the load current, IL. This decay time can
be approximated by the following equation:
t
DECAY = (CL
V)/I
L
The output disable time t
DIS is the difference between
t
is the interval from when the reference signal switches to
when the output voltage decays –V from the measured
output high or output low voltage. t
DECAY is calculated with
test loads C
L and IL, and with –V equal to 0.5 V.
Output Enable Time
Output pins are considered to be enabled when they have
made a transition from a high impedance state to when they
start driving. The output enable time t
ENA is the interval from
when a reference signal reaches a high or low voltage level
to when the output has reached a specified high or low trip
point, as shown in the Output Enable/Disable diagram
(Figure 30). If multiple pins (such as the data bus) are
enabled, the measurement value is that of the first pin to
start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular
system, first calculate t
DECAY using the equation given above.
Choose –V to be the difference between the
ADSP-21160M’s output voltage and the input threshold for
the device requiring the hold time. A typical –V will be 0.4 V.
C
L is the total bus capacitance (per data line), and IL is the
total leakage or three-state current (per data line). The hold
time will be t
DECAY plus the minimum disable time (i.e.,
t
DATRWH for the write cycle).
Table 30. External Power Calculations (3.3 V Device)
Pin Type
# of Pins
% Switching
× C
× f
× VDD
2
= PEXT
Address
15
50
× 44.7 pF
× 12.5 MHz
× 10.9 V
= 0.046 W
MS0
1
0
× 44.7 pF
× 12.5 MHz
× 10.9 V
= 0.000 W
WRx
2
–× 44.7 pF
× 25 MHz
× 10.9 V
= 0.024 W
Data
64
50
× 14.7 pF
× 12.5 MHz
× 10.9 V
= 0.064 W
CLKOUT
1
–× 4.7 pF
× 25 MHz
× 10.9 V
= 0.001 W
P
EXT = 0.135 W
Figure 30. Output Enable/Disable
RE F E R E NCE
SIG NA L
tDIS
O UT P UT S T AR T S
DR IV IN G
V OH (MEASURED) – DV
V OL (MEASURED) + DV
tMEASURED
V OH (MEASURED)
V OL (MEASURED)
2.0V
1.0V
HIG H -IM P E D AN CE S T AT E .
T EST CO ND ITIO N S CA USE T HISVO L T AG E
T O BE A P PR O X IM A TEL Y 1.5V
OUT P UT S T OP S
DR IV IN G
tDECAY
tENA
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相关代理商/技术参数 |
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| ADSP-21160MKBZ-80 | 功能描述:IC DSP CONTROLLER 32BIT 400 BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21160N | 制造商:AD 制造商全称:Analog Devices 功能描述:DSP Microcomputer |
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| ADSP-21160NCB-TBD | 制造商:AD 制造商全称:Analog Devices 功能描述:DSP Microcomputer |
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