参数资料
型号: ADSP-21160MKB-80
厂商: Analog Devices Inc
文件页数: 7/52页
文件大小: 0K
描述: IC DSP CONTROLLER 32BIT 400 BGA
产品培训模块: SHARC Processor Overview
标准包装: 1
系列: SHARC®
类型: 浮点
接口: 主机接口,连接端口,串行端口
时钟速率: 80MHz
非易失内存: 外部
芯片上RAM: 512kB
电压 - 输入/输出: 3.30V
电压 - 核心: 2.50V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 400-BBGA
供应商设备封装: 400-PBGA(27x27)
包装: 托盘
–15–
REV. 0
ADSP-21160M
Timing Specifications
The ADSP-21160M’s internal clock switches at higher fre-
quencies than the system input clock (CLKIN). To generate
the internal clock, the DSP uses an internal phase-locked
loop (PLL). This PLL-based clocking minimizes the skew
between the system clock (CLKIN) signal and the DSP’s
internal clock (the clock source for the external port logic
and I/O pads).
The ADSP-21160M’s internal clock (a multiple of CLKIN)
provides the clock signal for timing internal memory,
processor core, link ports, serial ports, and external port (as
required for read/write strobes in asynchronous access
mode). During reset, program the ratio between the DSP’s
internal clock frequency and external (CLKIN) clock
frequency with the CLK_CFG3–0 pins. Even though the
internal clock is the clock source for the external port, the
external port clock always switches at the CLKIN fre-
quency. To determine switching frequencies for the serial
and link ports, divide down the internal clock, using the
programmable divider control of each port (TDIVx/RDIVx
for the serial ports and LxCLKD1–0 for the link ports).
Note the following definitions of various clock periods that
are a function of CLKIN and the appropriate ratio control:
t
CCLK = (tCK) / CR
t
LCLK = (tCCLK)
LR
t
SCLK = (tCCLK)
SR
Where:
LCLK = Link Port Clock
SCLK = Serial Port Clock
t
CK = CLKIN Clock Period
t
CCLK = (Processor) Core Clock Period
t
LCLK = Link Port Clock Period
t
SCLK = Serial Port Clock Period
CR = Core/CLKIN Ratio (2, 3, or 4:1,
determined by CLK_CFG3–0 at reset)
LR = Link Port/Core Clock Ratio (1, 2, 3, or 4:1,
determined by LxCLKD)
SR = Serial Port/Core Clock Ratio (wide range,
determined by
CLKDIV)
Use the exact timing information given. Do not attempt to
derive parameters from the addition or subtraction of
others. While addition or subtraction would yield meaning-
ful results for an individual device, the values given in this
data sheet reflect statistical variations and worst cases. Con-
sequently, it is not meaningful to add parameters to derive
longer times.
See Figure 32 under Test Conditions for voltage reference
levels.
Switching Characteristics specify how the processor
changes its signals. Circuitry external to the processor must
be designed for compatibility with these signal characteris-
tics. Switching characteristics describe what the processor
will do in a given circumstance. Use switching characteris-
tics to ensure that any timing requirement of a device
connected to the processor (such as memory) is satisfied.
Timing Requirements apply to signals that are controlled
by circuitry external to the processor, such as the data input
for a read operation. Timing requirements guarantee that
the processor operates correctly with other devices.
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