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参数资料
| 型号： | ADSP-21160MKB-80 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 52/52页 |
| 文件大小： | 0K |
| 描述： | IC DSP CONTROLLER 32BIT 400 BGA |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 1 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | 主机接口，连接端口，串行端口 |
| 时钟速率： | 80MHz |
| 非易失内存： | 外部 |
| 芯片上RAM： | 512kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 2.50V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 400-BBGA |
| 供应商设备封装： | 400-PBGA（27x27） |
| 包装： | 托盘 |
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–9–
REV. 0
ADSP-21160M
Unused inputs should be tied or pulled to VDD or GND,
except for ADDR31–0, DATA63–0, FLAG3–0, and inputs
that have internal pull-up or pull-down resistors (PA, ACK,
BRST, PAGE, CLKOUT, MS3–0, RDx, WRx, DMARx,
DMAGx, DTx, DRx, TCLKx, RCLKx, LxDAT7–0,
LxCLK, LxACK, TMS, TRST and TDI)—these pins can
be left floating. These pins have a logic-level hold circuit
(only enabled on the ADSP-21160M with ID2–0 = 00x)
that prevents input from floating internally.
The following symbols appear in the Type column of
Table 2: A = Asynchronous, G = Ground, I = Input,
O = Output, P = Power Supply, S = Synchronous,
(A/D)= Active Drive, (O/D)= Open Drain, and
T = Three-State (when SBTS is asserted, or when the
ADSP-21160M is a bus slave).
Table 2. Pin Function Descriptions
Pin
Type
Function
ADDR31–0
I/O/T
External Bus Address. The ADSP-21160M outputs addresses for external memory and
peripherals on these pins. In a multiprocessor system, the bus master outputs addresses
for read/writes of the internal memory or IOP registers of other ADSP-21160Ms. The
ADSP-21160M inputs addresses when a host processor or multiprocessing bus master
is reading or writing its internal memory or IOP registers. A keeper latch on the DSP’s
ADDR31–0 pins maintains the input at the level it was last driven (only enabled on the
ADSP-21160M with ID2–0 = 00x).
DATA63–0
I/O/T
External Bus Data. The ADSP-21160M inputs and outputs data and instructions on
these pins. Pull-up resistors on unused DATA pins are not necessary. A keeper latch on
the DSP’s DATA63-0 pins maintains the input at the level it was last driven (only
enabled on the ADSP-21160M with ID2–0 = 00x).
MS3–0
O/T
Memory Select Lines. These outputs are asserted (low) as chip selects for the corre-
sponding banks of external memory. Memory bank size must be defined in the
SYSCON control register. The MS3–0 outputs are decoded memory address lines. In
asyn- chronous access mode, the MS3–0 outputs transition with the other address
outputs. In synchronous access modes, the MS3–0 outputs assert with the other address
lines; however, they de-assert after the first CLKIN cycle in which ACK is
sampled asserted.
RDL
I/O/T
Memory Read Low Strobe. RDL is asserted whenever ADSP-21160M reads from the
low word of external memory or from the internal memory of other ADSP-21160Ms.
External devices, including other ADSP-21160Ms, must assert RDL for reading from
the low word of ADSP-21160M internal memory. In a multiprocessing system, RDL
is driven by the bus master.
RDH
I/O/T
Memory Read High Strobe. RDH is asserted whenever ADSP-21160M reads from the
high word of external memory or from the internal memory of other ADSP-21160Ms.
External devices, including other ADSP-21160Ms, must assert RDH for reading from
the high word of ADSP-21160M internal memory. In a multiprocessing system, RDH
is driven by the bus master.
WRL
I/O/T
Memory Write Low Strobe. WRL is asserted when ADSP-21160M writes to the low
word of external memory or internal memory of other ADSP-21160Ms. External
devices must assert WRL for writing to ADSP-21160M’s low word of internal memory.
In a multiprocessing system, WRL is driven by the bus master.
WRH
I/O/T
Memory Write High Strobe. WRH is asserted when ADSP-21160M writes to the high
word of external memory or internal memory of other ADSP-21160Ms. External
devices must assert WRH for writing to ADSP-21160M’s high word of internal
memory. In a multiprocessing system, WRH is driven by the bus master.
PAGE
O/T
DRAM Page Boundary. The ADSP-21160M asserts this pin to signal that an external
DRAM page boundary has been crossed. DRAM page size must be defined in the
ADSP-21160M’s memory control register (WAIT). DRAM can only be implemented
in external memory Bank 0; the PAGE signal can only be activated for Bank 0 accesses.
In a multiprocessing system PAGE is output by the bus master. A keeper latch on the
DSP’s PAGE pin maintains the output at the level it was last driven (only enabled on
the ADSP-21160M with ID2–0 = 00x).
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相关代理商/技术参数 |
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| ADSP-21160MKBZ-80 | 功能描述:IC DSP CONTROLLER 32BIT 400 BGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
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