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参数资料
| 型号： | ADSP-21261SKSTZ150 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 42/44页 |
| 文件大小： | 0K |
| 描述： | IC DSP 32BIT 150MHZ 144LQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 60 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，SPI |
| 时钟速率： | 150MHz |
| 非易失内存： | ROM（384 kB） |
| 芯片上RAM： | 128kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
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ADSP-21261
Rev. 0
|
Page 7 of 44
|
March 2006
Serial Peripheral (Compatible) Interface
Serial peripheral interface is an industry-standard synchronous
serial link, enabling the ADSP-21261 SPI-compatible port to
communicate with other SPI-compatible devices. SPI is an
interface consisting of two data pins, one device select pin, and
one clock pin. It is a full-duplex synchronous serial interface,
supporting both master and slave modes. The SPI port can
operate in a multimaster environment by interfacing with up to
four other SPI-compatible devices, either acting as a master or
slave device. The ADSP-21261 SPI-compatible peripheral
implementation also features programmable baud rates up to
37.5 MHz, clock phases, and polarities. The ADSP-21261 SPI-
compatible port uses open-drain drivers to support a multimas-
ter configuration and to avoid data contention.
Parallel Port
The parallel port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16-
bit, the maximum data transfer rate is one-third the core clock
speed. As an example, a clock rate of 200 MHz is equivalent to
66M byte/s, and a clock rate of 150 MHz is equivalent to
50M byte/s.
Figure 3. ADSP-21261 Memory Map
RESERVED
0x0004 2000–0x0005 7F FF
BL OCK 0 ROM (1.5M BIT)
0x0005 8000–0x0002 FFFF
IOP REGIST ERS
0x0000 0000–0x0003 FFFF
BLOCK 0 SRAM (0.5M B IT)
0x0004 0000–0x0004 1FFF
RESERVED
0x0005 3000–0x0005 FF FF
BLOCK 1 SRAM (0.5M B IT)
0x0006 0000–0x0006 1FFF
BLOCK 1 ROM (1.5M BIT)
0x0007 8000–0x0007 DFFF
RESERVED
0x0007 E000–0x0007 FFFF
RESERVED
0x0006 2000–0x0007 7FFF
LONG WORD
ADDRESSING
RESERVED
0x0008 4000 - 0x000A FFF F
BLOCK 0 ROM ( 1.5M B IT)2
0x000B 0000–0x000B BFFF
IOP REGISTERS
0x0000 0000–0x0003 FFF F
BLOCK 0 SRAM ( 0.5M BIT)
0x0008 0000–0x0008 3FFF
RESERVED
0x000B C000–0x000B FF FF
BLOCK 1 SRAM (0.5M B IT)
0x000C 0000–0x000C 3FF F
BLOCK 1 ROM (1.5M BIT)3
0x000F 0000–0x000F BFFF
RESERVED
0x000F C000–0x000F FFF F
RESERVED
0x000C 4000–0x000E FF FF
NORMAL WORD
ADDRESSING
R ESERVED
0x0010 8000–0x0015 FFFF
BLOCK 0 ROM (1.5M BIT)
0x0016 0000–0x0017 7FFF
IOP REGISTERS
0x0000 0000–0x0003 FF FF
BLOC K 0 SRAM (0.5M BIT)
0x0010 0000–0x0010 7FFF
RESERVED
0x0017 8FFF–0x0017 FFFF
BLOC K 1 SRAM (0.5M BIT)
0x0018 0000–0x0018 7FFF
BL OC K 1 ROM ( 1.5M BIT)
0x001E 0000–0x001F 7FF F
RESERVED
0x0018 8000–0x001D FFFF
SHORT WORD
ADDRESSING
RESERVED
0x0020 0000–0x00FF FFFF
EXTERN AL DMA
AD DRESS SPACE1
0x0100 0000–0x02FF FFFF
RESERVED
0x0300 0000–0x3FF F F FFF
EXTERNAL MEMORY
SPACE
1 EXTERNAL MEMORY IS NOT DIRECTLY
A CCESSIBLE B Y T HE CORE. DMA MUST BE
U SED TO READ OR WRITE TO THIS MEM O R Y
US I N G T HE S P I O R P ARA L L E L P O R T .
2 BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE
( 0xA0000–0xA7 FF FF) .
3 BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE
( 0xE0000–0xE7 F FFF).
INTERNAL MEMORY
SPACE
R ESERVED
0x000
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