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| 型号： | ADSP-21261SKSTZ150 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/44页 |
| 文件大小： | 0K |
| 描述： | IC DSP 32BIT 150MHZ 144LQFP |
| 产品培训模块： | SHARC Processor Overview |
| 标准包装： | 60 |
| 系列： | SHARC® |
| 类型： | 浮点 |
| 接口： | DAI，SPI |
| 时钟速率： | 150MHz |
| 非易失内存： | ROM（384 kB） |
| 芯片上RAM： | 128kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 1.20V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-LQFP |
| 供应商设备封装： | 144-LQFP（20x20） |
| 包装： | 托盘 |
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ADSP-21261
Rev. 0
|
Page 13 of 44
|
March 2006
CLKIN
I
Input only
Local Clock In. Used in conjunction with XTAL. CLKIN is the ADSP-21261 clock input.
It configures the ADSP-21261 to use either its internal clock generator or an external
clock source. Connecting the necessary components to CLKIN and XTAL enables the
internal clock generator. Connecting the external clock to CLKIN while leaving XTAL
unconnected configures the ADSP-21261 to use the external clock source such as
an external clock oscillator. The core is clocked either by the PLL output or this clock
input depending on the CLKCFG1–0 pin settings. CLKIN may not be halted,
changed, or operated below the specified frequency.
XTAL
O
Output only2
Crystal Oscillator Terminal. Used in conjunction with CLKIN to drive an external
crystal.
CLKCFG1–0
I
Input only
Core/CLKIN Ratio Control. These pins set the start-up clock frequency. See Table 5
for a description of the clock configuration modes.
Note that the operating frequency can be changed by programming the PLL multi-
plier and divider in the PMCTL register at any time after the core comes out of reset.
RSTOUT/CLKOUT
O
Output only
Reset Out/Local Clock Out. Drives out the core reset signal to an external device.
CLKOUT can also be configured as a reset out pin (RSTOUT). The functionality can
be switched between the PLL output clock and reset out by setting Bit 12 of the
PMCTL register. The default is reset out.
RESET
I/A
Input only
Processor Reset. Resets the ADSP-21261 to a known state. Upon deassertion, there
is a 4096 CLKIN cycle latency for the PLL to lock. After this time, the core begins
program execution from the hardware reset vector address. The RESET input must
be asserted (low) at power-up.
TCK
I
Input only
3
Test Clock (JTAG). Provides a clock for JTAG boundary scan. TCK must be asserted
(pulsed low) after power-up or held low for proper operation of the ADSP-21261.
TMS
I/S
Three-state with
pull-up enabled
Test Mode Select (JTAG). Used to control the test state machine. TMS has a
22.5 k
Ω internal pull-up resistor.
TDI
I/S
Three-state with
pull-up enabled
Test Data Input (JTAG). Provides serial data for the boundary scan logic. TDI has a
22.5 k
Ω internal pull-up resistor.
TDO
O
Three-state4
Test Data Output (JTAG). Serial scan output of the boundary scan path.
TRST
I/A
Three-state with
pull-up enabled
Test Reset (JTAG). Resets the test state machine. TRST must be asserted (pulsed
low) after power-up or held low for proper operation of the ADSP-21261. TRST has
a 22.5 k
Ω internal pull-up resistor.
EMU
O (O/D)
Three-state with
pull-up enabled
Emulation Status. Must be connected to the Analog Devices DSP Tools product
line of JTAG emulators target board connector only. EMU has a 22.5 k
Ω internal pull-
up resistor.
VDDINT
P
Core Power Supply. Nominally +1.2 V dc and supplies the DSP’s core processor
(13 pins on the BGA package, 32 pins on the LQFP package).
VDDEXT
P
I/O Power Supply. Nominally +3.3 V dc (6 pins on the BGA package, 10 pins on the
LQFP package).
AVDD
P
Analog Power Supply. Nominally +1.2 V dc and supplies the DSP’s internal PLL
(clock generator). This pin has the same specifications as VDDINT, except that added
filtering circuitry is required. For more information, see Power Supplies on Page 8.
AVSS
G
Analog Power Supply Return.
GND
G
Power Supply Return. (54 pins on the BGA package, 39 pins on the LQFP package).
1 RD, WR, and ALE are continuously driven by the DSP and will not be three-stated.
2 Output only is a three-state driver with its output path always enabled.
3 Input only is a three-state driver, with both output path and pull-up disabled.
4 Three-state is a three-state driver, with pull-up disabled.
Table 2. Pin Function Descriptions (Continued)
Pin
Type
State During and
After Reset
Function
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相关代理商/技术参数 |
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| ADSP-21262 | 制造商:AD 制造商全称:Analog Devices 功能描述:SHARC Processor |
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| ADSP-21262SBBC-150 | 功能描述:IC DSP 32BIT 150MHZ 136-CSPBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:2 系列:StarCore 类型:SC140 内核 接口:DSI，以太网，RS-232 时钟速率:400MHz 非易失内存:外部 芯片上RAM:1.436MB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:-40°C ~ 105°C 安装类型:表面贴装 封装/外壳:431-BFBGA，FCBGA 供应商设备封装:431-FCPBGA（20x20） 包装:托盘 |
| ADSP-21262SBBCZ150 | 功能描述:IC DSP 32BIT 150MHZ 136-CSPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - DSP（数字式信号处理器） 系列:SHARC® 标准包装:40 系列:TMS320DM64x, DaVinci™ 类型:定点 接口:I²C，McASP，McBSP 时钟速率:400MHz 非易失内存:外部 芯片上RAM:160kB 电压 - 输入/输出:3.30V 电压 - 核心:1.20V 工作温度:0°C ~ 90°C 安装类型:表面贴装 封装/外壳:548-BBGA，FCBGA 供应商设备封装:548-FCBGA（27x27） 包装:托盘 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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