参数资料
型号: ADT7462ZEVB
厂商: ON Semiconductor
文件页数: 51/82页
文件大小: 0K
描述: BOARD EVALUATION FOR ADT7462
产品变化通告: MFG CHG Notification ADI to ON Semi
标准包装: 1
类型: 温度传感器
适用于相关产品: ADT7462
所含物品: 评估板
其它名称: EVAL-ADT7462EBZ
EVAL-ADT7462EBZ-ND
ADT7462
is 2/3 ? V CCP , the correct threshold for an AGTL + signal.
The THERM assert bits in Host Thermal Status Register 2
(0xB9) are set to Logic 1 whenever the THERM input is
asserted low. The THERM state bits in Host Thermal Status
Register 2 (0xB9) indicate that a high-to-low transition has
taken place on the THERM pin.
When the measured percentage exceeds the
corresponding percentage limit, the T1% bit in Host
Therma l Status Register 2 (0xB9) is asserted, and an
ALERT is generated (that is, if the mask bit is not set). If the
limit is set to 0x00, an ALERT is generated on the first
assertion. If the limit is set to 0xFF, an ALERT is never
TEMPERATURE
100 5 C
90 5 C
80 5 C
70 5 C
60 5 C
50 5 C
40 5 C
ALERT
THERM LIMIT
HIGH TEMP LIMIT
THERM LIMIT
HYSTERESIS
RESET BY MASTER
generated because 0xFF corresponds to the THERM input
being asserted all the time.
When THERM is configured as an input only, setting Bits
[4:1] of the THERM zone in the THERM1 configuration
register (0x0E) and the THERM2 configuration register
(0x0F) allows Pin 28/Pin 29 to operate as an I/O.
THERM Timer Limit Register
The THERM timer limit is programmed to Register 0x80
and Register 0x81. If THERM is asserted for longer than the
programmed percentage limit, then an ALERT is generated.
THERM
1
2
3
4
The limit is programmed as a percentage of the chosen
THERM timer window.
%Limit + 1 100 + 12.5%
12.5% + 32 decimal + 0 20 + 00100000
Figure 83. THERM Behavior
THERM Timer
The ADT7462 can also measure assertion times on the
THERM inputs as a percentage of a timer window. The timer
window for the THERM1 input is programmed using
Bits [4:2] of the THERM configuration register (0x0D). The
timer window for the THERM2 input is programmed using
Bits [7:5] of the THERM configuration register (0x0D).
Values from 0.25 sec to 8 sec are programmable (see
Table 31).
Table 31. THERM TIMER WINDOW
EXAMPLE: The THERM timer window is eight seconds,
and an ALERT should be generated if THERM is asserted
for more than one second.
8
The THERM timer limit register is an 8 ? bit register.
0 00 + 0%; 0 FF + 100%
Therefore, 1 LSB = 0.39%
0.39%
When the time window has elapsed, if the THERM limit
has been exceeded, then an ALERT is generated.
Code
000
001
010
011
100
101
110
111
THERM Timer Window
0.25 sec
0.5 sec
1 sec
2 sec
4 sec
8 sec
8 sec
8 sec
General-Purpose I/O Pins
The ADT7462 has eight open-drain GPIO pins. GPIO1 to
GPIO4 can be configured to enable event driven outputs
(EDOs), and GPIO5 and GPIO6 can act as EDOs, if the EDO
functionality is enabled. Two other GPIOs (GPIO7 and
GPIO8) are standard GPIO pins that are dedicated to
general-purpose logic input/output.
Each GPIO pin has five data bits associated with it: three
bits in a GPIO configuration register (0x09 and 0x0A), one
in the GPIO status register (0xBF), and one in the GPIO
mask register (0x36).
The assertion time as a percentage of the timer window is
stored in the THERM % on-time registers. This is a
cumulative sum of the percentage of time during the
THERM timer window that THERM is asserted. The %
on-time and associated timer limit registers are listed in
Table 32.
Table 32. THERM ON-TIME AND TIMER LIMIT
REGISTER
Setting a direction bit to 1 in a GPIO configuration register
makes the corresponding GPIO pin an output.
Clearing the direction bit to 0 makes the corresponding
GPIO pin an input.
Setting a polarity bit to 1 in a GPIO configuration register
makes the corresponding GPIO pin active high.
Clearing the polarity bit to 0 makes the corresponding
GPIO pin active low.
When a GPIO pin is configured as an input, the
Channel
THERM1
THERM2
% On-Time Register
0xAE
0xAF
% Timer Limit Register
0x80
0x81
corresponding bit in the GPIO status register is read-only,
and it is set when the input is asserted (“asserted” can be high
or low, depending on the setting of the polarity bit).
http://onsemi.com
51
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