参数资料
型号: ADT7462ZEVB
厂商: ON Semiconductor
文件页数: 52/82页
文件大小: 0K
描述: BOARD EVALUATION FOR ADT7462
产品变化通告: MFG CHG Notification ADI to ON Semi
标准包装: 1
类型: 温度传感器
适用于相关产品: ADT7462
所含物品: 评估板
其它名称: EVAL-ADT7462EBZ
EVAL-ADT7462EBZ-ND
ADT7462
When a GPIO pin is configured as an output, the
corresponding bit in the GPIO status register becomes
read/write. Setting this bit then asserts the GPIO output.
(Again, “asserted” can be high or low, depending on the
setting of the polarity bit.) The effect of a GPIO status
register bit on the ALERT output can be masked by setting
The polarity of the EDOs is set in the GPIO configuration
registers (0x09 and 0x0A).
Setting a polarity bit to 1 in one of the GPIO configuration
registers makes the corresponding GPIO pin active high.
Clearing the polarity bit to 0 makes it active low.
the corresponding bit in one of the GPIO mask registers.
When the pin is configured as an output, the
corresponding status bit is automatically masked to prevent
the data written to the status bit from causing an interrupt.
When configured as inputs, the GPIO pins can be connected
GPIO1
GPIO2
GPIO3
GPIO4
LATCH
EVENT
MASK
EDO (GPIO5)
EDO (GPIO6)
to external interrupt sources such as temperature sensors
with digital output.
EDO Circuitry
The ADT7462 has the added functionality that the
assertion of one of the four GPIOs (GPIO1 to GPIO4) can
be used to latch one of the two EDOs high or low. The
ADT7462 has two EDO event mask registers (0x37 and
0x38): one mask for each EDO. See Table 33 for an
explanation of event mask register functionality.
Figure 84. EDO Circuit
Bits [7:5] of each event mask register (0x37 and 0x38)
allow the EDO output to be driven high or low (depending
on the polarity bit of the configuration register) and latched
(depending on the EDO latch bit of the configuration
register), if the ADT7462 detects an overtemperature, an
over/undervoltage, or a fan failure condition.
Table 33. EDO CONTROL (MASK) REGISTER 0X37 AND REGISTER 0X38
Bit 7:
Overvoltage/
Undervoltage
0 = Drive Output X
1 = Ignore Event
Bit 6: THERM
0 = Drive Output X
1 = Ignore Event
Bit 5: Fan Fail
0 = Drive Output X
1 = Ignore Event
Bit 3
0
0
Bit 2
0
0
Bit 1
0
0
Bit 0
0
1
Behavior: What Drives and
Latches Output X (G = GPIO)
G4 or G3 or G2 or G1
G4 or G3 or G2
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
G4 or G3 or G1
G4 or G3
G4 or G2 or G1
G4 or G2
G4 or G1
G4
G3 or G2 or G1
G3 or G2
G3 or G1
G3
G2 or G1
G2
G1
GPIO Events Ignored by Output X
Table 33 shows that any of the four designated GPIO pins
can be used to set or reset either one of the two EDO outputs.
Using this functionality, it is possible to have the
ADT7462 drive LEDs or signals based on rules. For
example, if a GPIO1 (power fail), a GPIO2 (overcurrent), or
Other Digital Inputs
The ADT7462 contains other specific digital inputs that
can be found on PC motherboards. These inputs can be
monitored and configured for actions to occur on their
assertion.
an overtemperature condition occurs, EDO1 (power supply
fault LED) can be latched. This does not require software
handling and makes the part more autonomous.
http://onsemi.com
52
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